Abstract: A VCO supply voltage regulator includes a control voltage input, first and second supply voltage inputs, a regulated voltage output, a current source and an amplifier. The current source is coupled between the first voltage supply input and the regulated voltage output and has a bias input. The amplifier has an amplifier input coupled to the control voltage input, an amplifier output coupled to the bias input and a feedback input coupled to the regulated voltage output.

Abstract: An apparatus is described which determines the velocity of a fluid flow stream by measuring the frequency of vortex shedding from an obstruction in the fluid flow stream. A constant known as the Strouhal number is used to relate the measured vortex shedding frequency to the fluid flow velocity. The Strouhal number is a function of the Reynolds number for the obstruction, which is also a function of fluid flow velocity. Hence, an iterative technique is provided, first using an estimated Strouhal number to estimate the fluid flow velocity, using the estimated fluid flow velocity to estimate the Reynolds number, then using the Reynolds number to get a better estimate of the Strouhal number. The apparatus repeats this cycle until the estimate of the fluid flow velocity converges.

Abstract: The present invention is directed to a low-power input buffer comprising an inverter coupled to receive a first safe voltage range to a first node and coupled to provide an output signal, and a low-power circuit coupled to receive a second safe voltage range and coupled to control a voltage at the first node in response to the output signal and the second safe voltage range. The first and second safe voltage ranges preferably are equivalent. The low-power circuit includes series transistors coupled to the first node and responsive to the voltage at the output node. The low-power circuit further includes a transistor coupled between the first and second nodes and responsive to an input voltage. A method of operating an input buffer comprises the steps of pulling up a voltage of a first node in response to voltages of a second node and an output node and pulling down the voltage at the first node and the second node in response to an input voltage to provide low power consumption and a high impedance input.

Abstract: An integrated circuit includes a substrate and at least two circuits, such as a digital circuit and an analog circuit. The substrate is preferably derived from a bulk substrate wafer. The integrated circuit preferably comprises at least two islands in the substrate for noise isolation between the circuits. The two islands are buried-layers that are implanted, by preference, using conventional MeV techniques. A method of manufacturing an integrated circuit includes a substrate and at least two circuits. The method comprises the step of implanting at least two islands in the substrate for noise isolation between the circuits. The implanting is accomplished by conventional masking and high-energy implantation, such as MeV.

Abstract: A novel integrated circuit structure, and process for making same, is disclosed wherein a tapered or gradient doped profile region is provided in a semiconductor substrate between the heavily doped drain region and the channel region in the substrate comprising an MOS device. In the process of the invention, a re-entrant or tapered gate electrode, resembling an inverted trapezoid, is used as a mask during a first doping step at a dosage level higher than normally used to form a conventional LDD region. This doping step forms a doped region having a dopant gradient which gradually increases in dosage level with distance from the channel region. Conventional oxide spacers may then be formed on the sidewalls of the gate electrode followed by conventional high level doping to form the heavily doped source and drain region in the unmasked portions of the substrate between the oxide spacers and the field oxide isolation.

Abstract: A semiconductor integrated circuit is made by a process including the formation on a surface of a semiconductor integrated circuit processing wafer of a layer of material applied to the wafer by plasma enhanced chemical vapor deposition (PECVD). The layer of material may include plural sub-layers, the thicknesses of which are additive to result in the thickness of the layer of material itself. The sub-layers of material may have non-uniform thicknesses across a dimension of the processing wafer because of compromises in the process which are necessary to control various parameters of the material layer other than its thickness. These non-uniformities of thickness of the sub-layers may be controlled to offset one another so that the resulting layer of material has a substantially uniform thickness across the dimension of the processing wafer.

Abstract: A method for depositing a planar dielectric layer between metal traces of a metallization layer of a semiconductor wafer is disclosed. A thin layer of light absorbing material is deposited on the surface of a wafer prior to the formation of metal lines on an overlying patterned metallization layer. A source of directed radiation preferentially heats the light absorbing material while the metal lines reflect the directed radiation and remain largely unheated, thereby allowing dielectric material to be evenly deposited between the metal traces. An isolation layer which insulates the metal traces from the layer of light absorbing material may be required. In some applications, the source of directed radiation is a laser source with a wavelength in the infrared range, and the light absorbing material is a material which absorbs light in this range.

Abstract: The present invention comprises a method for controlling a threshold voltage through a semiconductor substrate of a first conductivity type (the type being an n- or p- type in a MOSFET) without the need for a blanket implant for either long or short channel devices. A gate structure having opposed lateral edges is formed adjacent a surface of the semiconductor substrate and over a channel region of the substrate. The substrate is rotated around a rotation axis normal to the surface of the substrate to a first rotation position. Ions of a first conductivity type are then implanted into the channel region, using the gate structure as a mask, at an oblique angle relative to the surface normal of the substrate. The substrate is then rotated to a second rotation position approximately 180 degrees from the first rotation position. Ions of the first conductivity type are then implanted into the channel region, using the gate structure as a mask, at the oblique angle relative to the surface of the substrate.

Abstract: A microelectronic cell includes a semiconductor substrate, an active area formed in the substrate, a gate formed in the active area, and a first contact formed in the active area. The contact has a width D perpendicular to a reference axis defined in the active area, and is spaced from the reference axis by a minimum spacing E. The gate includes a first section which extends substantially parallel to the reference axis, the first contact being disposed between the first section and said reference axis, the first section being spaced from the first contact by a minimum spacing A; a second section which extends substantially parallel to and is spaced from said reference axis by a minimum spacing C<(A+D+E), the second section being spaced from the first section along said reference axis; and a third section which extends at an angle to the reference axis and joins adjacent ends of the first and second sections.

Abstract: Apparatus and associated methods for improving I/O performance in a computing system which includes one or more MPUs and one or more IOPs. I/O requests are queued by a requesting MPU in a memory shared with one or more IOPs. Each IOP is associated with a queue. Each IOP may continue processing queued I/O requests after completing processing on an earlier request. In addition, each MPU is associated with a queue shared with the IOPs. When an IOP completes processing of an I/O request, a completion message is added to the requesting MPU's queue and an interrupt is generated for that MPU. The MPU services all completion messages in its queue when the interrupt is processed. A threshold value is associated with each MPU queue. The threshold value indicates the minimum number of completed I/O requests required before an interrupt request is generated to the MPU.

Abstract: An initial placement of cells for an integrated circuit chip is decomposed into a hierarchial order of groups of cells. The groups are routed simultaneously using parallel processors, and the results are recomposed to provide a global routing that provides a detailed mapping of cell interconnect congestion in the placement. Areas of high congestion are identified, and a congestion reduction algorithm is applied using the parallel processors to alter the placement in these areas simultaneously. The overall fitness of the placement is then computed, and if it has not attained a predetermined value, the steps of identifying congested areas and applying the congestion reduction algorithm to these areas are repeated. The cumulative error created by altering the placement without repeating the global routing is estimated, and if it exceeds a predetermined value, the global routing is also repeated.

Abstract: A method for maximizing effectiveness of parallel processing, using multiple processors, to achieve an optimal cell placement layout on an integrated circuit (IC) chip is disclosed. The method requires the cells of the IC to be assigned to one of the multiple processors in a manner to balance the work load among the multiple processors. Then, the affinity of the cells to each of the multiple processors is determined. The affinity of the cells, including the conflict reduction factors and work load balancing factors, is used to reassign the cells to the processors. The cell affinity calculation and the processor reassignment are repeated until no cells are reassigned or for a fixed number of times. The assignment of the cells to the multiple processors and subsequent reassignments of the cells based on affinity of the cells to the processors reduces or eliminates the problems associated with prior parallel cell placement techniques.

Abstract: A video device is provided having a more efficient Reed-Solomon decode methodology. The Reed-Solomon decoder advantageously receives pre-indentified error locations and, given those locations, focuses entirely upon correcting (as opposed to detecting) erroneous symbols at those locations. A noise detector is used to identify erroneous symbol intervals, and forwards information signifying erroneous symbol locations or erases symbols within those locations. The detected error locations are forwarded to the Reed-Solomon decoder which then adds (or subtracts) correction quantities to symbols within those locations. Given pre-identified error locations, the Reed-Solomon decoder can correct double the number of corrupted symbols. The decoder, herein provided, therefore proves beneficial in high speed decoding of video signals sent from a video device having forward error correction.

Abstract: A process which is capable of forming shallow source/drain regions in a silicon substrate and a doped gate electrode by implantation of cobalt silicide contacts of uniform thickness previously formed on the substrate followed by diffusion of the dopant into the substrate to form the desired source/drain regions, and into the polysilicon gate electrode to provide the desired conductivity is described.

Abstract: Methods of planarizing one or more layers having an irregular top surface topology in a semiconductor device based on an underlying MOS structure are disclosed. Methods of creating doped wells or regions for the underlying MOS structure are also disclosed, using thick oxide growths on the surface of the substrate to mask implantation of ions into the wells. A technique for creating a pair of adjacent complementary oppositely-doped wells, such as for a CMOS structure, using a thick oxide growths as a mask is also disclosed. One of the methods of planarizing the one or more layers involves depositing, densifying and re-flowing a layer of glass on top of the topological layer. Another method of planarizing the one or more layers involves depositing, densifying and chemical-mechanically polishing the deposited and densified glass, thereby avoiding an additional temperature cycle (i.e., for re-flowing the glass) which would adversely affect underlying diffusions.

Abstract: A system for optimally locating cells on the surface of an integrated circuit chip is presented herein. The system comprises constructing a plurality of neighborhoods containing elements positionally related to one another; initially evaluating the lowest level of region hierarchy; iteratively developing a logical one-dimensional preplacement of elements on said surface; performing an affinity driven discrete preplacement optimization; evaluating whether a highest level of regional hierarchy has been attained; iteratively performing a dispersion driven spring system to levelize cell density and an unconstrained sinusoidal optimization; executing a density levelizing procedure; iteratively optimizing while controlling element densities; removing element overlap; iteratively optimizing for desired spacing between elements, adjusting element spacing, and permuting elements; locating elements on grid lines; and iteratively performing a functional sieve crystallization.

Abstract: An interconnect bump is formed on a substrate structure of a flip-chip microelectronic integrated circuit by sputtering a metal base layer on the substrate, and then forming a copper standoff on the base layer. A solder cap is formed on the standoff having a peripheral portion that extends laterally external of the standoff. The peripheral portion of the cap is used as a self-aligned mask for a photolithographic step that results in removing the metal base layer except under the standoff and the cap. The cap has a lower melting point than the standoff. Heat is applied that is sufficient to cause the cap to melt over and coat the standoff and insufficient to cause the standoff to melt. The peripheral portions of the cap and the base layer that extend laterally external of the standoff cause the melted solder to form into a generally hourglass shape over the standoff due to surface tension.

Abstract: A remote connection digital processing device with network capability includes on a single chip asynchronous transfer mode (ATM) network protocol processing system interconnection circuits and Motion Picture Experts Group (MPEG) decoder circuits. The ATM interconnection circuits include a physical-layer medium dependent (PMD) unit connected to an ATM network. A transmission convergence (TC)/Framer unit is connected to the PMD unit. An ATM segmentation and reassembly (SAR) unit is connected to the PMD unit. Packet conversion logic is coupled to the ATM SAR unit for converting ATM packets to MPEG format. The MPEG decompression decoder circuits include a demodulator decryption unit coupled to the packet conversion logic. A video decoder is coupled to the demodulator decryption unit. An audio decoder is coupled to the demodulator decryption circuit. A display is coupled to the video decoder. Audio output devices are coupled to the audio decoder.

Abstract: A process for manufacturing a modular multi-pin package for an integrated circuit die is formed of standardized parts and a redesigned, integrated circuit specific circuit substrate possessing a design pattern for providing electrical connection between die pads and output pins. The substrate includes a pattern of electrically conductive traces each terminating in a die pattern at an interior portion of the substrate and terminating in a pattern of pin connecting pads at a peripheral portion of the substrate. A pin holding frame is formed with a plurality of holes in which are inserted a selected number and pattern of package terminal pins, each having a shank protruding outwardly from the pin holder for connection to external circuits or components and each having an inner head pressed against one of the pin connecting pads of the substrate circuit traces.

Abstract: A multi-sided, integrated circuit die includes a plurality of read only memory (ROM) circuits, positioned only at the corners of the die, to simplify qualification testing of new package designs. During qualification testing, electrical and environmental stresses are applied to the package and die combination. The package and die are electronically evaluated at predetermined intervals to determine whether a failure has occurred during testing. When a failure occurs during testing, the package and die are diagnosed to isolate and determine the cause or source of the failure. Package design parameters are adjusted accordingly to reduce or eliminate the occurrence of the failures. An optional 12-bit counter is fabricated onto the die for each ROM circuit to exercise the ROM during qualification testing. An optional process monitor is also fabricated onto the die for each ROM circuit to determine the strength of the fabrication process and the resulting quality of circuit elements produced therefrom.