Abstract: The present invention concerns a method for eliminating or reducing clock skew introduced by differing signal propagation delays across a data bus. At high bus clock frequencies the time delay differences caused by path length differences can be catastrophic and must be eliminated by expensive layout techniques. An input/output (I/O) architecture is proposed here which tailors a delay to each individual data line, and thereby aligns all the incoming data. Furthermore, a clock signal is provided to indicate the optimal data sampling time. In the described embodiment, this circuit enables the transmission of four 32 bit words in parallel in one clock cycle of a 250 MHz processor.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: Apparatus for use in cooling an integrated circuit structure. The apparatus includes a heat sink having a first portion configured for thermal engagement with an integrated circuit device and a second portion configured for the dissipation of heat into an ambient fluid, such as air. The heat sink is made from a powdered metal which, in one preferred embodiment, includes copper. The heat sink may be formed from the plurality of discrete layers, each layer having a button projecting from one surface, and a depression formed in an opposing surface. The depression is configured to receive a projecting button portion from another layer. In an alternative embodiment the heat sink includes a plurality of plugs projecting from the generally flat surface.

Abstract: An integrated circuit package includes a heatspreader which is formed to have a centrally disposed recessed portion between planar surfaces, and flex tape extending from the planar surfaces into the centrally disposed surface. A semiconductor chip is mounted on the centrally disposed surface between the flex tape, and wire bonds interconnect bonding pads on the chip to the metal interconnect patterns on the flex tape. Plastic molding or epoxy is then applied to encapsulate the chip and wire bonding in the centrally disposed planar surface of the heat spreader. The package is then readily mounted on a motherboard using solder balls.

Abstract: A system for defining a cut point dividing a plurality of cells located on the surface of a semiconductor chip is disclosed herein. The surface has at least one region located thereon. The system comprises dividing each region into subregions, computing the capacity of each subregion, finding the maximum and minimum cell locations within each region, dividing the range spanning the maximum and minimum cell locations into a plurality of subintervals, calculating an index for each cell based on the subinterval containing the cell, accumulating cell heights for each subinterval, determining the values of cell heights for each region as the sum of cell heights for all prior regions, locating the minimum index such that the cell heights for each region are most closely proportional to the capacity of the associated subregion, and finding the cut line based on said minimum index and the maximum and minimum cell locations.

Abstract: Disclosed is a method and apparatus for designing re-useable interfacing logic hardware shells which provide interface functions between a hardware core and one or more busses. An interface logic hardware shell provides previously characterized, tested and implemented interface logic designs for use in future applications with little or no redesign. The hardware circuitry (cells) of which such shells are comprised includes circuitry for bus interface units, memory interface units, buffers, and bus protocol logic. The cores for which the shells provide interface functions include CPU cores, memory cores, digital video decoding cores, digital audio decoding cores, ATM cores, Ethernet cores, JPEG cores and other data processing cores.

Abstract: The subject invention is directed to a method for producing semiconductor wafers using a simplified hole interconnect process. These wafers include at least one interconnect layer located on a contact or via layer. As contrasted with the semiconductor wafers produced according to the prior art method described above, the contact or via layer of this invention includes a plurality of patterned openings formed therein which are in substantial alignment without offset with each other.

Abstract: Microelectronic devices are formed on a substrate of an integrated circuit. An electrically conductive ground or power plane, and an ElectroStatic Discharge (ESD) protection layer are formed on the substrate. Terminals such as solder ball or wire bond pads are formed on the substrate, and are electrically connected to the devices. The protection layer is patterned such that portions thereof are disposed between the terminals and the plane to define vertical electrical discharge paths. The protection layer is formed of a material such as SurgX.TM. which is normally dielectric, and is rendered conductive in the discharge paths by an electrostatic potential applied to the terminals during an ESD event to shunt the electrostatic potential from the terminals to the plane. Alternatively, the protection layer can be formed between the terminals to define lateral discharge paths.

Abstract: An MPEG decoder system and method for performing video decoding or decompression which includes a unified memory for multiple functions according to the present invention. The video decoding system includes transport logic, a system controller, and MPEG decoder logic. The video decoding system of the present invention includes a single unified memory which stores code and data for the transport, system controller and MPEG decoder functions. The single unified memory is preferably a 16 Mbit memory. The MPEG decoder logic includes a memory controller which couples to the single unified memory, and each of the transport logic, system controller and MPEG decoder logic access the single unified memory through the memory controller. The video decoding system implements various frame memory saving schemes, such as compression or dynamic allocation, to more efficiently use the memory.

Abstract: A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip having digital interface signals. The tuner chip is configured to receive the digital signals at a reduced peak-to-peak amplitude to reduce the digital interference noise in the tuner chip. The digital signals may also have a limited slew rate to further reduce the digital interference noise. The tuner chip is configured to convert a receive signal to a baseband signal, and the demodulator/decoder chip is configured to convert the baseband signal to a decoded signal.

Abstract: The present invention provides a method and apparatus for conditioning a polishing pad in which slurry is directed under pressure at the polishing pad. Additionally, energy (i.e., ultrasonic energy) may be added to the slurry as it is directed towards the polishing pad, wherein embedded material in the polishing pad is removed or dislodged.

Abstract: One or more non-overlapping moving windows are positioned over a placement of cells for an integrated circuit chip to delineate respective subsets of cells. A fitness improvement operation such as simulated evolution is performed on the subsets simultaneously using parallel processors. The windows are either moved to specifically identified high interconnect congestion areas of the placement, or are moved across the placement in a raster type pattern such that each area of the placement is processed at least once. Exchange of misplaced cells between subsets can be accomplished by dimensioning the windows and designing the window movement pattern such that the subsets overlap. Alternatively, such exchange can be accomplished by using two sets of windows of different sizes. As yet another alternative, the improvement operation can allow misplaced cells to move to a border area outside a window.

Abstract: A system for optimizing the density of cells located on a surface of a semiconductor chip divided into a plurality of rectangular regions is provided herein. The corners of these regions define nodes. The system comprises computing an average local cell density for regions adjacent to each node and deforming these regions by relocating nodes to positions that minimize a cost function associated with the densities of the new deformed regions bordering the relocated nodes.

Abstract: A method and apparatus for dissipating heat from a semiconductor device. A heat sink embodying the method includes an exterior surface contoured to better facilitate heat dissipation and/or direct a flow of air or fluid over the heat sink. In one embodiment, the heat sink includes a heat sink layer formed from a powdered metal. In another embodiment, the heat sink layer is contoured with a selected combination of bumps, indentations and holes. In yet another embodiment, the heat sink includes a stack of such heat sink layers which are mechanical; interfitted and thermally coupled.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: The present invention discloses a system to reverse-synthesize a gate level netlist definition of an integrated circuit (IC) design to corresponding register transfer level (RTL) definition of the same circuit. The typical process to implement an integrated circuit is to complete the RTL design first, which is then used, to generate gate level netlist definition, and eventually, a layout level design targeted to a particular process technology. The RTL design definitions, being a general description of the circuit, may be ported to different process technologies. However, the gate netlist level design, being a more specific or lower level definition of the circuit, is not easily ported to other integrated circuit design processes. To port a gate netlist level design to another process technology, the gate netlist should be converted, or reverse-synthesized back to a RTL level design.

Abstract: An apparatus and method are presented for polishing removal of a select amount of material from a surface of a semiconductor wafer. The apparatus includes a polishing pad having a moveable planar polishing surface. The surface of the semiconductor wafer and a surface of at least one sacrificial member are retained against the polishing surface. A measurement system determines an amount of material removed from the surface of the sacrificial member. The measurement system includes a sensor unit for each sacrificial member coupled to a computational device. Each sensor unit is used to determine the amount of material remaining at the surface of the corresponding sacrificial member. The computational device determines the amount of material removed from the surface of each sacrificial member based upon the amount of material remaining at the surface. The amount of material removed from the surface of the sacrificial member corresponds to an amount of material removed from the surface of the semiconductor wafer.

Abstract: A system and method are presented for forming a grid array device package around an integrated circuit (i.e., chip), the packaged device incorporating electromagnetic shielding. Embodiments of the packaged device include an integrated circuit, a substrate, and a thermally and electrically conductive heat spreader. The integrated circuit includes multiple input/output (I/O) pads on an underside surface divided into a central portion and a surrounding peripheral portion. Members of the central portion are connected to corresponding bonding pads on an upper surface of the substrate using the controlled collapse chip connection (C4) method. Members of the peripheral portion are connected to an electrical ground potential. One end of a grounding lead is attached to each member of the peripheral portion of the I/O pads such that the remaining free end extends outward from the integrated circuit. The grounding leads may be, for example, metal foil strips or wires.

Abstract: Hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic include two registers that surround the Domino logic to allow that logic to be tested. One register receives an input test vector, loaded directly through a primary set of inputs or by a serial scan chain if the register inputs are not directly accessible. The second register latches the results of the test vector application. The register contents can either be read directly through a primary set of outputs if there is no static CMOS logic between the register outputs and a primary set of circuit outputs, or scanned out of the second register using a serial scan chain. Domino scan flip-flops, which reduce transistor count over conventional static scan flip-flops, can be used in the Domino logic as sequential elements to implement multiple logic functions.

Abstract: Methods operable in a SCSI RAID subsystem to enable improved portability in host based RAID management programs. RAID management programs which provide an administrative user interface for managing the operation and configuration of a RAID subsystem have traditionally communicated with the RAID system using control function calls (ioctl) through the operating system's device driver. Ioctl function calls are notoriously non-standardized among different operating systems and even among different versions of certain operating systems. The methods of the present invention are operable within a RAID subsystem to enable use of standardized read and write system function calls to the device driver for communication with a control port within the RAID subsystem. A special LUN is reserved for such read and write administrative calls. The special control port LUN processes the read and write calls to perform the desired RAID management functions on behalf of the management program on an attached host computer.