Abstract: A method and apparatus for positioning a cell in a cell placement for an integrated circuit chip such that a total wirelength for interconnect nets that are connected to said cell is substantially minimum includes constructing bounding boxes around the interconnect nets with the cell excluded respectively. A median interval of the bounding boxes within which the total wirelength is substantially invariant is computed, and the cell is positioned in the median interval. Another optimization methodology, such as for minimizing interconnect congestion, is then applied to compute and position the cell in an optimum location in the median interval.

Abstract: A method for reducing the effect of a noise impulse in a digitizing panel which includes a resistive layer is disclosed. The method includes the steps of generating a signal when an object is in proximity to the digitizing panel, amplifying the signal with an amplifier, detecting the presence of the noise impulse coupled to the resistive layer, and disconnecting an input of the amplifier from the resistive layer in response to detecting the noise impulse. In addition, a digitizing panel is disclosed which includes a resistive layer for providing a signal when an object is in proximity to the digitizing panel.

Abstract: A method for maximizing effectiveness of parallel processing, using multiple processors, to achieve an optimal cell placement layout of a core area of an integrated chip is disclosed. The method requires the core area to be divided into preferably a grid of rectangular regions. Then, the rectangular region is sequenced such that each region of the sequence is not adjacent to the previous or the next region of the sequence, and is sufficiently far from the previous and from the next region of the sequence such that when multiple processors are assigned to consecutive regions of the sequence to perform cell placement algorithms, area-conflicts are minimized eliminating the need to limit the distances the cells may be moved.

Abstract: A tag memory circuit includes an address index input, an address offset input and an integrated adder and pre-decode circuit. The integrated adder and pre-decode circuit has a first addend input coupled to the address index input, a second addend input coupled to the address offset input, and a pre-decoded sum output. A final row decode and word line driver circuit is coupled to the pre-decoded sum output and generates a word line output which is coupled to the address inputs of a tag memory array. The data outputs of the tag memory array are coupled to a sense amplifier.

Abstract: A bridge translates addresses between a first bus and a second bus, with a larger address space capability. The bridge stores "high address" information and combines that information with address information from a device on the first bus when the device desires to transfer information from the first bus to the second bus. The bridge accesses high address information using information identifying the device.

Abstract: A high speed digital video network apparatus is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits. The interconnection includes a packet conversion logic which converts between a network protocol, such as Asynchronous Transfer Mode (ATM) packets, and the data protocol used to handle large data streams, such as Motion Picture Experts Group (MPEG) packets.

Abstract: Separate and distinct conductive layers for power and ground are insulated from one another and a patterned signal conductive layer to form a flexible substrate for mounting a semiconductor die in a semiconductor device assembly. TAB technology is utilized to produce an assembly that has superior electrical characteristics because power and ground is conducted on separate low impedance conductive layers. The power and ground leads connecting the semiconductor die and external circuits are selected from the signal trace layer, cut bent downward and attached by bonding to the respective power or ground layer. A tool is disclosed for cutting the selected leads. A method of attaching solder balls to a TBGA film using solder flux and photoimageable solder resist definition is also disclosed.

Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.

Abstract: An Inverse Discrete Cosine Transform processor employs symmetry and reusable elements to use a fewer number of gates while maintaining processing speed at an acceptable level. Even and odd sums are generated simultaneously by even and odd sum generators. A butterfly operation is then performed on the on the even and odd sums to produce pairs of transformed elements simultaneously. For an 8.times.8 block, the even and odd sum generators can be designed to a generate four pairs of even and odd sums sequentially. This design allows a single row or column of eight elements to be processed in 4 clock cycles. A horizontal transformation on all eight rows of the block can be performed in 32 cycles. A vertical transformation can then be performed by storing the transformed rows in a second memory, reading out columns from the second memory, and using the same hardware to generate the sums and perform the butterfly operation on the columns.

Abstract: An integrated circuit phase-locked loop includes a phase/frequency detector, a charge pump, and a voltage-controlled oscillator (VCO) which are coupled together in series. The VCO has first and second VCO control inputs, and has a VCO output which is coupled to the phase/frequency detector. An off-chip loop filter input is coupled between the charge pump and the first VCO control input for coupling to an off-chip loop filter. An on-chip loop filter is coupled between the first VCO control input and the second VCO control input. The VCO has a lower voltage-to-frequency gain from the first VCO control input to the VCO output than from the second VCO control input to the VCO output.

Abstract: A process for forming improved metal silicide contacts over the gate electrode and source/drain regions of MOS devices of an integrated circuit structure formed in a silicon substrate is described. The metal silicide contacts are formed by first forming a silicon oxide layer over exposed portions of the silicon substrate and over exposed surfaces of previously formed polysilicon gate electrodes. Silicon nitride sidewall spacers are then formed over the oxide on the sidewalls of the gate electrode by depositing a silicon nitride layer over the entire structure and then anisotropically etching the silicon nitride layer. Source/drain regions are then formed in the silicon substrate adjacent the nitride spacers and the structure is then contacted with an oxide etch to remove oxide from the upper surface of the gate electrode and the substrate surface over the source/drain regions.

Abstract: A Video Display FIFO includes a circular buffer and counters that allow the FIFO to properly recover from data alignment problems caused by FIFO underflow. A pair of counters store read and write pointers, which indicate the addresses of data read from and written into the buffer. Another counter stores a count of data in the buffer. Buffer underflow causes the count to go negative and the read pointer to advance ahead of the write pointer. Data written into the buffer while the total count is negative is not read out of the buffer. This allows alignment of the data to be restored.

Abstract: A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: A voltage comparator circuit includes a comparator 42 having a first comparison input, a second comparison input and first and second switched current memories 52, 58 (e.g., switched FETs) connectable, respectively, to the first and second comparator inputs for input voltage offset compensation. In use, during a storage phase, a current value is stored in the switched current memory for each of the first and second comparison inputs and, during a comparison phase, the stored current values are used to compensate for voltage offsets between the comparison inputs.

Abstract: A DBS receiver front end which converts the received signal directly to the baseband representation and maintains a high performance with a new techniques for tracking and counteracting frequency drift and I/Q angular error. The DBS receiver front end comprises a tuner and a demodulator/decoder. The tuner receives a high frequency signal and converts it to a baseband signal having a frequency offset error. In one embodiment, the DBS receiver front end includes a demodulator/decoder which receives the baseband signal and produces a compensation signal for canceling the frequency offset error. The demodulator/decoder performs the frequency-offset error compensation digitally. The demodulator/decoder includes an A/D converter which over-samples (samples at a rate of more than two samples per symbol period) the baseband signal and converts it to digital form.

Abstract: VLSI I/O structures to reduce the effects of simultaneous switching noise (SSN) on output driver circuits and enhance electrostatic discharge immunity, while reducing chip area, in both input receiver circuits and output driver circuits include improved transistors having deep-junction drain and a multi-cascaded, resistive deep-junction source structure.

Abstract: A reusable hardware layout ("core") for performing some, but not all, MPEG and AC-3 audio decoding functions. Specifically, the audio core performs matrixing and windowing operations of MPEG and AC-3 decoding. The disclosed audio core design includes a data path, a control logic unit, an input RAM interface (for controlling an input RAM), an output RAM interface (for controlling an output RAM), a ROM, a ROM addressing logic unit, and a registers interface. The input RAM and the output RAM are located outside of the audio core. The control logic unit specifies in which state of multiple states the audio core currently resides, with each of the multiple states specifying one function or group of functions of either the MPEG or AC-3 decoding process. The control logic unit includes an MPEG state machine for generating MPEG state and cycle count information and an AC-3 state machine for generating AC-3 state and cycle count information.

Abstract: A method for creating a shell to represent a functional block of an IC design comprising of a plurality of interconnected functional blocks. The critical information from a synthesized gate level block is retained in the shell such that when analyzing the static characteristics of another block connected to the block now represented by the shell the analysis is still accurate. At a hierarchial level the present invention provides a method for analyzing the functional blocks of an IC design such that the memory requirement for storing the information of the functional blocks of the IC design is reduced as well as a decrease in run time.

Abstract: A system for improving the position of cells located on a surface of a semiconductor chip having at least one region located thereon is disclosed herein. The system calculates affinities for relocating the cell to an alternate region, computes a first threshold, and repositions all cells having a maximum affinity greater than the first threshold to the region providing the maximum affinity for the cell.