Abstract: Hybrid CMOS circuit configurations that include both static CMOS logic and Domino CMOS logic include two registers that surround the Domino logic to allow that logic to be tested. One register receives an input test vector, loaded directly through a primary set of inputs or by a serial scan chain if the register inputs are not directly accessible. The second register latches the results of the test vector application. The register contents can either be read directly through a primary set of outputs if there is no static CMOS logic between the register outputs and a primary set of circuit outputs, or scanned out of the second register using a serial scan chain. Domino scan flip-flops, which reduce transistor count over conventional static scan flip-flops, can be used in the Domino logic as sequential elements to implement multiple logic functions.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The decompression of the immediate field used for load/store instructions having the global pointer register as a base register is optimized for mixed compressed/non-compressed instruction execution. The immediate field is decompressed into a decompressed immediate field for which the most significant bit is set.

Abstract: A circuit for testing a semiconductor device, which has an oscillator for producing pulses when energized. A control circuit receives a test signal, a clock signal having pulses, and a reset signal, and energizes the oscillator for a predetermined length of time in response to the test signal. A counter detects the pulses produced by the oscillator, and produces counter signals which indicate the number of pulses detected by the counter. An output detector receives the counter signals and produces an output signal when the counter signals indicate that the number of pulses detected is equal to a predetermined number. However, the number of pulses produced by the oscillator during the predetermined length of time is preferably less than the predetermined number. The control circuit provides the clock signal to the counter after the predetermined length of time, until the output of the output detector indicates that the predetermined number of pulses has been detected.

Abstract: A system for ascertaining the penalty associated with relocating a cell located on a surface of a semiconductor chip to an alternate location is disclosed herein. The system comprises a region capacity calculator for determining a capacity of cells which will fit in the current region, a height capacity calculator for determining the sum of heights for all cells located in each region, a basic penalty calculator which computes a basic penalty associated with relocating the cell to another location based on the capacity and heights of cells for the current region and the capacity and heights of cells in the proposed region, and a total penalty calculator for computing the total penalty associated with the basic penalty, penalties associated with multiple regions, and cell capacity for the current cell.

Abstract: A circuit and method which enables storage of more than two logic states in a memory cell by selectively setting threshold voltages of transistors in a memory array according to the present invention. In one embodiment, a memory circuit includes an array of storage transistors. Each storage transistor has a gate connected to an associated read line. When a read line is asserted, the current which flows through a selected storage transistor is indicative of the stored logic state. The current through each transistor is individually selected by setting the threshold voltage of each storage transistor during manufacture. Different transistors in the array are configured with differing threshold voltages to thereby represent different storage states. An analog-to-digital (A/D) converter is coupled to the selected storage transistor so as to sense the current and determine the state represented.

Abstract: The port in a packet network switching system that a packet should be associated with is determined by retrieving packet address information for a packet that is to be transmitted. A predetermined number of bits from the packet address information is selected to use a hash key, which is used to compute a table address. The contents of the table at that address are compared with the packet address information. If it matches, the packet is transmitted over the port associated with that particular destination address. If it does not match, the table address is incremented by one, and the contents of the new table location identified by the incremented address are compared with the packet address information. A high speed digital video network apparatus which utilizes the hashing function is implemented on a single integrated circuit chip, and includes a network protocol processing system interconnection, compression/decompression circuits, and encoder/decoder circuits.

Abstract: A differential signal receiver circuit includes a first differential stage receiving input differential signals, a second differential stage receiving shifted differential signals and summing stage summing outputs of the first and second differential stages. Preferably the summing stage is formed by a wired-OR connection between the first and second differential stage outputs. The circuit finds application in digital systems for receiving data transmitted between digital equipment.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A method an corresponding apparatus for improving the input/output performance of a computer system under the control of a multi-tasking, multi-threaded operating system. In particular, the invention provides an apparatus and method to interleave contiguous DMA scatter/gather sub blocks of a PRD table corresponding to a first I/O channel with contiguous DMA scatter/gather sub blocks of a PRD table corresponding to a second I/O channel, using a single data manager, while maintaining maximum media bandwidth. DMA block transfers are scheduled by the single data manager based on the availability of data from the I/O devices' buffer memories, thus minimizing both media or network idle time as well as minimizing I/O bus idle time. Near maximum aggregate bandwidth of multiple I/O buses and their associated devices is obtained. The apparatus and method thus provides significant performance advantages over prior techniques having two I/O channel systems implemented with a single data manager.

Abstract: An information system and method for reducing workload load on servers in an information system network. The system defines a group of interconnected clients which have associated cache memories. The system maintains a shared group cache look-up table for the group having entries which identify data items cached by the clients within the group and identify the clients at which the data items are cached. Each client in the group has access to the group cache look-up table, and any client or group can cache any data item. The system can include a hierarchy of groups, with each group having a group cache look-up table. The group cache look-up tables minimize requests for data items outside the groups and greatly minimize the service load on servers having popular data items.

Abstract: A digital synthesizer for producing a digital frequency signal includes a phase accumulator for repeatedly accumulating a phase value to generate samples of a digital sawtooth signal and a look-up table of digital samples for converting the digital sawtooth signal to a digital waveshape signal. In order to reduce the effect of the quantization of the digital samples, the synthesizer also includes a randomizer for applying a randomizing factor to output digital samples for forming the digital frequency signal. The randomizer includes a randomizing factor generator connected to receive P bits of each digital sample for generating at least one randomizing bit and an summer for summing the remaining N bits of the digital sample and the at least one randomizing bit to generate a digital waveshape sample of the digital frequency signal.

Abstract: The present invention includes at least two variable-resistive devices, such as transistors, coupled to a resistive device, such as a resistor. The transistors are configured so that feedback voltage generated by respective currents of the transistors is applied to the gate of at least one of the transistors. The electrical characteristics of the other transistor changes proportionately greater than the characteristics of the one transistor. With this configuration, a variation-compensated current device is provided.

Abstract: A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.

Abstract: A circuit for multiplying a clock signal. The circuit includes a phase interpolator having two inputs for receiving complementary clock signals. The output of the phase interpolator is connected to an input in an exclusive OR gate. One of the two complementary input signals also is sent into the exclusive OR gate, wherein a multiplied clock signal is generated at the output of the exclusive OR gate.

Abstract: A method of providing etched alignment marks on a semiconductor workpiece that has a substantially planar surface, such as one that has been polished, for supporting accurate alignment of the workpiece in subsequent process operations. The surface of the semiconductor workpiece includes two layers of materials that abut at the workpiece surface. For example, the workpiece may include a layer of insulative material such as silicon dioxide forming several vias and a layer of conductive material such as tungsten forming plugs in the vias. The method includes etching the substantially planar surface to reduce a height of one of the materials below the height of the other material. For example, the tungstein plugs can be etched to a height that is below the height of the surrounding silicon dioxide. The location where the silicon dioxide abuts the tungsten produces a small bump. This bump then serves as an alignment mark for subsequent operations.

Abstract: A circuit for embedding within a SCSI control device for generating REQ or ACK signals in a flexible manner as required for SCSI synchronous data transfer mode. The circuit of the present invention utilizes a single counter and associated logic to provide flexible waveform generation of the REQ or ACK signal in a SCSI control device. The counter value counts up from zero and is compared against one of two values applied to a comparator. The first value is the desired period (duration) of the assertion of the REQ/ACK signal. When this count value is reached, the counter is restarted, the REQ/ACK signal is de-asserted, and the second count value--the de-assertion time--is applied to the comparator. When the second count is reached, the cycle starts over. An enable and reset signal allow other portions of the SCSI control device to start, stop, and reset the counter circuit of the present invention as required for SCSI synchronous data transfer controls.

Abstract: A polishing composition is shown which includes (1) a polishing media particle; (2) a film forming binder for suspending the particle and forming a temporary film on an exposed surface of the workpiece, the temporary film being dissolvable in a subsequently applied polishing wash, whereby the polishing media particle is freed to polish the workpiece; (3) a solvent for suspending the polishing media particle in the film forming binder to facilitate forming the temporary film; and (4) a wetting agent to improve the wettability of the composition on the exposed surface of the workpiece.

Abstract: Formation of a barrier region in a single crystal group IV semiconductor substrate at a predetermined spacing from a doped region in the substrate is described to prevent or inhibit migration of dopant materials from an adjacent doped region through the barrier region. By implantation of group IV materials into a semiconductor substrate to a predetermined depth in excess of the depth of a doped region, a barrier region can be created in the semiconductor to prevent migration of the dopants from the doped region through the barrier region. The treatment of the single crystal substrate with the group IV material is carried out at a dosage and energy level sufficient to provide such a barrier region in the semiconductor substrate, but insufficient to result in amorphization (destruction) of the single crystal lattice of the semiconductor substrate.

Abstract: A first array of elongate pads is formed on a first surface, such as that of an integrated circuit substrate, and a second array of elongate pads is formed on a second surface, such as that of a printed circuit board. An array of solder balls are reflow attached to the pads of the first array and then to the pads of the second array, to thereby electrically connect the substrate to the printed circuit board. The reflow solder balls thereby conform to the elongate shapes of the pads to be configured like truncated ellipsoids. Due to the surface tension forces between the pads and the balls therebetween, the "ellipsoids" advantageously have a high standoff. Also, the pads on each of the sides of the perimeter of the array are aligned longitudinally perpendicular to the respective sides. Thereby, wide channels between adjacent elongate pads are defined, through which one or more additional traces can advantageously be routed on the surface between the pads.

Abstract: A slew rate control circuit for an output circuit of an integrated circuit includes an input node for obtaining an input signal and an output node for providing an output signal. A first stage of the control circuit includes at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor are connected together to the input node. The first main terminal of each at least one transistor are connected to a voltage rail. The second main terminal of each at least one transistor is connected to the output node through its own individual resistor. One or more subsequent stages of the control circuit each contain at least one transistor having a control terminal and first and second main terminals. The control terminals of each at least one transistor in each one or more subsequent stages of the control circuit are connected together to a control node driven from the control terminals of the preceding stage through at least one inverter.