Abstract: A DIP integrated circuit package is disclosed which includes a trench-type DRAM and an associated non-symmetric lead frame having one or more Y-shaped leads which branch in the direction of die I/O pads. Such non-symmetric lead frames allow multiple use of pin spacing (i.e., one pin may be used to connect to widely spaced I/O pads on the DRAM die). Further, such structures serve to dissipate the generated heat, and thereby reduce noise, in high density trench-type DRAMs, such as 64 Mbit DRAMs. The lead frame is provided as a DIP lead frame which has no die attach pad and is wire bonded to I/O pads of the integrated circuit that are provided along a center line on the chip.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: A memory circuit which uses multiple storage mechanisms in each of its memory cells. In one embodiment, the memory circuit comprises a memory cell array and a data sense module. Each cell of the array includes a first, second and third transistors, and a capacitance. The first transistor has a first gate coupled to a first word line, a floating gate which stores a first charge, a first source coupled to a first data line, and a first drain. The second transistor has a second gate coupled to the first drain, a second source coupled to a second word line, and a second drain. The third transistor has a third gate coupled to a third word line, a third source coupled to the second drain, and a third drain coupled to a second data line. The capacitance is coupled between ground and the third source. The capacitance stores a second charge when the second word line is asserted and the third word line is de-asserted. The second gate stores a third charge when the first word line is de-asserted.

Abstract: A multiprocessing system includes a plurality of data processing subsystems each coupled to an interprocessor communications bus through a corresponding interprocessor communications interface. The interprocessor communications interface corresponding to each data processing subsystem includes a receive FIFO buffer unit, a transmit FIFO buffer unit, and a control circuit. When a data processing subsystem desires to transfer data to another processing subsystem, the data processing subsystem packetizes the data in a variable word-length transfer packet which includes a header having a size field and a target field. The data processing subsystem causes the transfer packet to be stored within the transmit FIFO buffer unit. When a valid transmit packet is stored with the transmit FIFO buffer of the interprocessor communications interface corresponding to a particular processing subsystem, the associated control unit requests mastership of the interprocessor communications bus and transmit packet.

Abstract: A ball grid array package utilizes solder balls having central cores of a material with a higher melting point than solder material surrounding the core. When the ball grid package and motherboard assembly are heated to the melting point of the solder material, the cores remain solid and function as spacers in preventing direct contact of the package surface and the motherboard surface, thus preventing molten solder from being squashed and flowing to adjacent ball contacts.

Abstract: A ball grid array package in which one or more conductive rings are positioned on a surface of the package substrate along with solder bond contacts on the surface of the substrate to facilitate the interconnection of wire bonds to an integrated circuit chip on the surface of the substrate. The use of rings allows for better distribution of power to the chip since a plurality of wires can be connected between the chip and the conductive rings for power distribution. The rings create a different shelf for the power and ground bonds on the substrate, and by providing a vertical separation between the surfaces of the rings and bonding pads on the surface of the substrate more bonds in the package can be accommodated.

Abstract: A uniformly doped polysilicon gate electrode of an MOS device forming a part of an integrated circuit structure on a semiconductor substrate is formed by first depositing a very thin layer of amorphous or polycrystalline silicon, e.g., from about 2 nm to about 10 nm, over a gate oxide layer. The thin layer of silicon layer is then exposed to a nitrogen plasma formed from N.sub.2 at a power level sufficient to break the silicon--silicon bonds in the thin layer of silicon, but insufficient to cause sputtering of the silicon to cause a barrier layer of silicon and nitrogen to form at the surface of the thin silicon layer. Further silicon, e.g., polysilicon, is then deposited over the barrier layer to the desired thickness of the polysilicon gate electrode. The gate electrode is then conventionally doped, i.e.

Abstract: Signals (including probes) from an external system are selectively connected to a plurality of unsingulated dies on a semiconductor wafer with a minimum number of connections and an electronic selection mechanism resident on the wafer. The electronic selection mechanism is connected to the individual dies by conductive lines on the wafer. The electronic selection mechanism is capable of providing the external signals (or connecting the external probe) to a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively provide signals to the unsingulated dies.

Abstract: A random number generating apparatus for an interface unit of a Carrier Sense with Multiple Access and Collision Detect (CSMA/CD) Ethernet data network. The interface unit includes a transmit backoff unit for implementing a backoff algorithm in response to a network collision signal and a random number. The apparatus comprises a dual mode random number generator and a multiplexer for switching the random number generator between modes in accordance with the serial address bits of a data packet being processed by the interface unit. The random number generator includes a 25 stage linear feedback shift register. The multiplexer has two signal inputs connected to outputs of the 18th and 22nd stages of the shift register respectively, a switch input connected to receive the serial address bits and an output connected in circuit to an input of the shift register.

Abstract: An initial placement of cells, and a routing including wires interconnecting the cells, is provided for a microelectronic integrated circuit. A grid is defined as including a plurality of first gridlines that extend parallel to a first axis, and a plurality of second gridlines that extend parallel to a second axis that is angularly displaced from the first axis. The cells are represented as vertices located at intersections of first and second gridlines, and the wires are represented as edges that extend along the first and second gridlines. Clusters of vertices are created such that each cluster includes vertices located on a respective first gridline. A "cover" is computed as including a minimum block of clusters that are connected to all other clusters by wires extending along the second gridlines. Clusters outside the cover are spatially reordered along the second axis away from the cover in descending order of numbers of wires extending from the clusters along the second gridlines.

Abstract: A trench etching process is disclosed in which a substrate is etched under conditions that promote forward sputtering of mask material in a plasma reactor having at least three electrodes. The forward sputtering impedes etching of trench sidewalls by depositing a protective layer of mask material on the sidewalls of a trench being formed. By controlling the amount of forward sputtering, one can control the trench profile and aspect ratio (depth to width). By employing forward sputter etching in a three or more electrode reactor, trenches of less than one micron in width and having aspect ratios of at least 2.5:1 are formed. Such trenches are used in trench capacitors of high density DRAMs. A disclosed plasma reactor includes a grounded first electrode which forms part of the reactor's enclosure, a coiled second electrode disposed above and separated from the reactor enclosure by a dielectric shield, and a planar third electrode located below the substrate to be etched.

Abstract: A digital computer includes a processor, a memory and a program which operate in combination for inputting a placement of cells for an integrated circuit chip, and a netlist of wiring nets interconnecting the cells. The placement is divided into a plurality of contiguous regions, and cell densities in the regions are computed in accordance with locations of the cells in the placement. Wiring densities in the regions are computed in accordance with the locations of the cells and the netlist. The shapes of the regions are altered to produce altered regions such that cell densities and wiring densities in the altered regions are more level or uniform. The placement is then altered such that the cells occupy locations in the altered regions which are relative to their locations in the original regions. The porosities of the cells can also be computed and used in the computation of the region shapes.

Abstract: A system for computing an affinity for relocating a cell from a location on a surface of a semiconductor chip is disclosed herein. Each cell may be associated with a net connecting a plurality of cells. The system first partitions the surface into a number of regions and computes capacities of lines dividing the regions and number of nets crossing the lines. The system then calculates penalties based on the number of net crossings and the capacities of lines and determines the total affinity based on relative improvements for lines crossed by the nets.

Abstract: A video decoder system for reconstructing, storing and retrieving bidirectionally predictive-coded (B) frames for display including pull-down conversion includes a reconstruction unit for reconstructing the frames, where the reconstruction unit reconstructs the top-upper field of every other frame twice. The frame is conceptually divided into four sections, including top-upper, top-lower, bottom-upper and bottom-lower sections. A memory having only three segments for storing pixel data is provided, where each segment is sized to store any one of the frame sections. A segmentor receives and separates the pixel data according to the top and bottom fields for each section of each frame, and stores pixel data from the top field into one segment pixel data from the bottom field into another segment. The segrnentor initially selects any two segments for the upper half of the first frame, and then selects a segment being retrieved for display and the third segment for the bottom half of the first frame.

Abstract: A method for determining the thickness of a film in a film stack using reflectance spectroscopy is provided in which one of the films in the stack has unknown optical constants. Conventional methods of using reflectance measurements to determine the thickness of a film require knowledge of the thicknesses and optical constants of all underlying films. An embodiment involves forming a test layer across a substrate having a known thickness and known optical constants. The thickness of the layer is determined using reflectance measurements. A first layer of the same material is then formed across a second layer at the same conditions that the test layer was formed. Thus, the test layer and the first layer can be assumed to have the same thicknesses. A spectral response curve may be determined for the first layer. The first layer is then processed so that its thickness is no longer known.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A conversion system for converting run-level pairs into variable length codes (VLCs) for purposes of compression, where each run-level pair includes a run and level value derived from scanning blocks of DCT coefficients. Each run value is provided to a programmable memory, which stores a segment address table comprising a list of base addresses, where a base address is included for each valid run value. An adder is provided for adding the base address to the level value of the run-level pair for determining a VLC address. The VLC address is provided to another programmable memory, which stores a table of VLCs, where the VLCs are grouped according to corresponding run values into a plurality of run segments, where each run segment corresponds to one run value and where each group of VLCs are ordered according to level values. The VLCs are preferably organized in ascending order based on the level values.

Abstract: A tape ball grid array (TBGA) package, and a method of making a TBGA package, includes the use of a metal or other stiffener affixed to a flexible tape on which conductive traces connect contact points on an integrated circuit (IC) chip with an array of solder balls. The stiffener is perforated with a pattern of small vent holes. The TBGA package materials are hygroscopic. When the TBGA package is heated during 2nd level packaging, e.g., during solder reflow, moisture absorbed within the hygroscopic materials evaporates and the resulting water vapor is able to escape through the vent holes, rather than becoming trapped within the IC package and introducing various 2nd level packing failure modes.

Abstract: Described is an portion of an integrated circuit structure formed on a semiconductor substrate which provides electrostatic discharge (ESD) protection, utilizing an SCR structure, and also inhibits latchup of the SCR structure. The integrated circuit structure comprises an ESD protection device and an adjoining driver section matched together so that the width dimension of the ESD protection device matches the sum of the length of the adjacent driver section plus twice the width of a doped portion of the substrate forming a guard ring surrounding the driver section. When the length dimension of the MOS structure of the driver section is so maximized by further repeating of the source/gate/drain regions, the physical width dimension of the MOS structure of the driver section may be reduced without reducing the effective width of the MOS structure of the driver section, i.e., the effective width of the MOS structure remains sufficient to permit the required amount of power to be handled by the driver section.

Abstract: A test circuit is provided for detection of data retention faults and cell stability faults of a memory array, such as a static random access memory (SRAM). The memory array test circuit comprises a weak write test circuit, a memory array address decoder, a microprocessor and display unit. During testing of the memory array, the weak test circuit controls the address decoder to decrease the voltage on the word lines so that it is less than the threshold voltage of the memory array transistors. The microprocessor then writes an inverted data to the memory array and then reads it. The read inverted data is sent to the display unit for comparison with a known template. By comparing the read inverted data to the template, defective memory cells can be identified.