Abstract: A test circuit is provided for detection of data retention faults and cell stability faults of a memory array, such as a static random access memory (SRAM). The memory array test circuit comprises a weak write test circuit, a memory array address decoder, a microprocessor and display unit. During testing of the memory array, the weak test circuit controls the address decoder to decrease the voltage on the word lines so that it is less than the threshold voltage of the memory array transistors. The microprocessor then writes an inverted data to the memory array and then reads it. The read inverted data is sent to the display unit for comparison with a known template. By comparing the read inverted data to the template, defective memory cells can be identified.

Abstract: Described is an portion of an integrated circuit structure formed on a semiconductor substrate which provides electrostatic discharge (ESD) protection, utilizing an SCR structure, and also inhibits latchup of the SCR structure. The integrated circuit structure comprises an ESD protection device and an adjoining driver section matched together so that the width dimension of the ESD protection device matches the sum of the length of the adjacent driver section plus twice the width of a doped portion of the substrate forming a guard ring surrounding the driver section. When the length dimension of the MOS structure of the driver section is so maximized by further repeating of the source/gate/drain regions, the physical width dimension of the MOS structure of the driver section may be reduced without reducing the effective width of the MOS structure of the driver section, i.e., the effective width of the MOS structure remains sufficient to permit the required amount of power to be handled by the driver section.

Abstract: A semiconductor die is disposed on a side of an optically-transmissive preformed planar structure (interposer), and an optical element is disposed on an opposite side of the interposer. The interposer may be provided with through holes extending at least partially into the die side, and electrical probes in the through holes, for making contact to raised conductive bumps on the die. The interposer may be provided with raised portions for locating the optical element at a predetermined distance away from the die. The interposer may be provided with darkened areas for preventing light from impacting selected areas of the die.

Abstract: A simulation based power analysis tool extracts "expected" current waveforms from simulation results. These expected waveforms are then used to represent the power consumption for a corresponding circuit cell or groups of cells from which the waveform is derived. The expected waveform is a statistical representation of a current derived over a number of cycles. The expected waveform is derived by recording the starting time of each power arc with respect to a tool defined clock period. The width of the waveform is derived from the average current, propagation delay and intrinsic delay for arc. The expected waveform can take several forms depending on the accuracy required. Each form has a corresponding memory storage requirement. The starting time for each arc can be stored, which yields the most accurate "true" expected waveform. Alternatively, the minimum, maximum and average starting times for a given power arc can be stored from which a "weighted min-max" expected waveform can be constructed.

Abstract: An integrated circuit device package of this invention includes a flexible substrate having an upper patterned insulative layer, and a lower patterned conductive layer including a plurality of package leads. An integrated circuit die is fixed within a void of the upper surface of the flexible substrate. Electrical connections between the integrated circuit die and the package leads are provided. A rigid upper protective layer is present. The rigid upper protective layer encloses the integrated circuit die, and at least partially covers the top surface of the upper insulative layer. The semiconductor device package further comprises a rigid or semi-rigid metal lower protective layer opposite the upper protective layer including a ground plane proximal to the electrical leads and a power plane distal to the leads. Methods of production are also given.

Abstract: A method is provided for operating a scan chain in a semiconductor device having a plurality of serially connected logic blocks, an output from a first logic block being coupled to an input of a first latch, the output from the first latch being coupled to the input of a second logic block, an output of the second logic block being coupled to an input of a second latch, the method comprising: detecting a test enable signal; if the test enable signal is active: detecting the output of the first latch, and setting the output of the second latch to the same state as the detected output of the first latch, independently of the state of the output of the second logic block; if the test enable signal is inactive: setting the output of the second latch responsive to the output of the second logic block.

Abstract: A high speed Advanced Programmable Interrupt Controller (APIC) system includes a plurality of local units for prioritizing and passing interrupts, an Input/Output (I/O) unit for feeding interrupts to the local units, and a serial link data transmission system for interconnecting the I/O unit and the local units. The I/O unit and each local unit have a parallel I/O interface.

Abstract: A system for determining an affinity associated with relocating a cell located on a surface of a semiconductor chip to a different location on the surface is disclosed herein. Each cell may be part of a cell net containing multiple cells. The system initially defines a bounding box containing all cells in the net which contains the cell. The system then establishes a penalty vector based on the bounding box and borders of a region containing the cell, computes a normalized sum of penalties for all nets having the cell as a member, and calculates the affinity based on the normalized sum of penalties.

Abstract: A shared memory fabric architecture for asynchronous transfer mode (ATM) switches including a multi-dimensional array of electrically interconnected N*M switch modules, where N>>M. The fabric architecture also includes input ports for providing cells to the array of switch modules. The input ports operate at a predetermined speed S. The fabric architecture additionally includes memory devices electrically connected to the array to provide a hierarchical memory structure at each switch module. The memory devices include on-chip, high-speed memory devices operating at a high-speed memory speed of N*S and off-chip, low-speed memory devices operating at a low-speed memory speed of (Y+M)*S, where Y<<N.

Abstract: A method for producing a relatively thin titanium nitride barrier layer in an integrated circuit is presented. The titanium nitride layer may be utilized in a tungsten plug interconnection by providing a semiconductor wafer with a conducting layer covered by an insulating layer. The insulating layer is patterned and etched to form contact holes or vias. A layer of titanium is deposited on the surface of the wafer including the sidewalls and bottom of the via. A relatively thin titanium nitride layer is then formed on the titanium layer. The formation of the titanium nitride layer includes growing titanium nitride by a reaction of a nitrogen-bearing species with the titanium layer. The titanium nitride layer prevents the underlying titanium layer from reacting with the subsequent tungsten layer which is deposited on the wafer to fill the via. The tungsten layer is then etched so that the tungsten remaining forms a plug interconnection between conducting layers.

Abstract: A method derives edge extensions for wavelet transforms and inverse wavelet transforms of two-dimensional images. The method overcomes the necessity of side computations by treating the two-dimensional matrix of values as a one-dimensional array of values. The use of a one-dimensional array reduces the required flushing and loading of registers by allowing the flushing and loading to be performed in between frames, rather than in between rows or columns of the matrix.

Abstract: Various forms of micromachined electrostatic microconveyors and useful devices based thereon are described. In one embodiment, a tube shaped conveyor is formed by disposing conductors circumferentially about the exterior surface of the tube. The tube is formed of an insulating material (e.g., silicon dioxide). Driving voltages are applied in staggered phase to selected ones of the conductors to provide a travelling electrostatic wave within the tube. Charged particles (or fluid or gas) can be propelled through the tube electrostatically by "riding" the travelling wave. Various aspects of the invention are directed to apparatus making use of the microconveyor to convey particles, gas ions, etc. Apparatus is described for using gas pressure resulting from the transport of gas ions to do mechanical work (i.e., to operate mechanical actuators.

Abstract: A single ended bit line sensor includes a single ended bit line input, a sensor output, an inverting amplifier, a non-inverting amplifier and a differential amplifier. The inverting amplifier is coupled to the single ended bit line input and has a first voltage output. The noninverting amplifier is coupled to the single ended bit line input and has a second voltage output. The differential amplifier has first and second amplifier inputs coupled to the first and second voltage outputs, respectively, and has an amplifier output coupled to the sensor output.

Abstract: An electrostatic discharge (ESD) protection circuit includes first and second supply terminals, a current source, a shunt transistor, an inverter and a voltage level shifting device. The shunt transistor is coupled between the first and second supply terminals and has a control terminal. The inverter includes an input coupled to the current source, an output coupled to the control terminal of the shunt transistor and pull-up and pull-down transistors coupled between the first and second supply terminals. The pull-up and pull-down transistors have control terminals which are coupled to the input. The voltage level shifting device is coupled between the input and the control terminal of one of the pull-up and pull-down transistors.

Abstract: The present invention provides a local rip-up and reroute (LRR) method to reduce the number of open nets after the initial routers have been applied. Two main tasks are performed under this method. The first task is to identify a locally blocked pin and rip up wire segments in an area around the cell having the locally blocked pin. The second task is to reroute the now freed locally blocked pin. In the first task, an open net is read from the list of open nets. The pins of this open net are identified and determined if they are locally blocked. A pin is considered as locally blocked if a routing path, starting from the pin, cannot be found within N grid point expansions. If a pin is locally blocked, segments of wires within or at the boundary of a predefined bounding box are removed (or ripped-up)--except for two situations. The first exception is that a wire that is connected to a pin is not ripped-up.

Abstract: An interposer (preformed planar structure) is disposed between a die and a substrate (which may be another die). Through holes in the interposer facilitate controlled formation of electrical connections between the die and the substrate. In one embodiment, the through-holes in the interposer are filled flush with a resilient plastic conductive material and pressed against raised conductive structures on the die and substrate. The die, interposer, and substrate are maintained in electrical contact under compression. The compressing force can be removed to replace the die. In another embodiment, the interposer has embedded conductive elements which make contact with selected connections between the die and the substrate. Electrical connections between the conductive elements can be selectively effected to provide for "re-wiring" of connections to the die and substrate.

Abstract: A random verification environment for verifying a semiconductor device includes a hardware engine programmed to include a random input generator that builds a set of test vectors. A first memory connected between the hardware engine and the semiconductor device stores the set of test vectors and supplies the set of vectors to the semiconductor device under the control of a first state machine generated by the hardware device. A second memory connected to the semiconductor device receives output signals from the semiconductor device in response to input test vectors. A random test iterator in the hardware engine provides a first state machine and also provides a second state machine that writes the signals output from the semiconductor device to the second memory. The test vectors are input to the semiconductor device at a rate equal to the operating rate of the semiconductor device. An expected output generator is arranged to receive the test vectors from the first memory.

Abstract: A system and method for using a BIST generator and a BIST compactor to characterize the propagation delay time of a high-speed embedded cores and integrated circuits in general. In one embodiment, an external clock is provided having a positive edge and a negative edge. The BIST generator and test compactor is configured to apply a set of test inputs to the integrated circuit in response to the positive edge, and the BIST compactor is configured to latch a set of outputs from the integrated circuit in response to the negative edge, and determine if the set of outputs represent a valid test result. The validity determination is monitored, and as long as the test result is valid, it is determined that the propagation delay time is less than the time interval between the positive and negative transitions. The propagation delay time can then be measured by reducing the time interval until invalid test results appear.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arrangement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: Disclosed is a reusable hardware layout ("core") for performing some, but not all, MPEG-2 video decoding functions. The information content of the core may be stored on a machine readable media and includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the video core architecture. The disclosed video decoder core design specifies that at least the following MPEG-2 functions are performed by the hardware: inverse scan, inverse quantization, inverse discrete cosine transform, half pel compensation, and merge. Other MPEG-2 functions such as motion vector decoding, variable length decoding, and run level decoding are not performed by hardware video cores fabricated in accordance with video core design.