Abstract: A method of cutting a plate-like wafer, particularly a semiconductor wafer, while removing a deposited material from along a scribe line. The deposited material having a width generally greater than the width of the saw blade. The method includes making one scribing cut to one side of the scribe line, making a second scribing cut to the other side of the scribe line, and making a severing cut along the scribe line to dice the wafer.

Abstract: A package for mounting a semiconductor device to a circuit board. An insulating substrate is provided, which has at least one layer, and provides rigidity to the package. A plurality of electrically conductive contacts are disposed on the top surface of the substrate, receive the semiconductor device, and make electrical contact between the semiconductor device and the substrate. A plurality of electrically conductive through-holes are formed in the substrate, and extend from the top surface of the substrate to the bottom surface of the substrate. The through-holes make electrical connection between all of the layers of the substrate. Electrical interconnections between the contacts and the through-holes are provided by a plurality of electrically conductive traces. A z-conductive layer is attached to the bottom surface of the substrate.

Abstract: A phase locked loop includes a voltage controlled oscillator (VCO) for generating output VCO pulses. A frequency divider divides the VCO pulses by a variable number to produce frequency divided pulses whose phase is compared with that of input reference pulses by a phase detector. An update pulse is produced by the phase comparator having a pulsewidth corresponding to the detected phase difference. A pulse generator generates a train of update pulses having a combined pulsewidth equal to the pulsewidth of the update pulse, with the update pulses being substantially equally distributed within each period of the reference pulses to produce low output ripple. The update pulses are integrated by a loop filter to produce a D.C. control voltage that controls the VCO to vary the frequency of the VCO pulses such that the phase difference is adjusted toward zero. The frequency divider comprises a binary counter and a controller that enable the frequency divider to divide by a number N that is not a power of 2.

Abstract: A process for designing an integrated circuit chip s comprises specifying a plurality of regions on the chip in which a plurality of objects are to be placed, such that there are more of the objects than the regions, and specifying penalties for the objects to be placed in the regions respectively. The objects can be microelectronic cells, interconnect wiring segments, etc. An assignment of the objects to the regions is constructed, and a number of objects for movement between the regions is selected. An optimal permutation of movement of the selected number of objects between the regions is computed such that a cost corresponding to the total penalties for the assignment is maximally reduced, and the assignment is modified by moving the selected number of objects through the optimal permutation. The process steps are repeated iteratively such that a maximum number of objects which will produce a maximal reduction in cost is moved during each iteration.

Abstract: A CMOS DRAM integrated circuit includes paired P-type and N-type wells in a substrate. The wells are fabricated using a self-aligning process. Similarly, FETs of the DRAM circuit are fabricated in the wells of the substrate using a self-aligning process to provide FETs of opposite polarity in a DRAM which may have paired memory cells and dummy cells for symmetry of circuitry. One or more layers having an irregular top surface topology may be planarized using mechanical or chemical-mechanical polishing of the topological layer.

Abstract: A cell placement for a microelectronic integrated circuit includes a plurality of cells interconnected by nets of wiring. A method for estimating routing density in the placement includes superimposing a pattern of contiguous tiles over the placement, with each of the tiles having edges. Bounding boxes are constructed around the nets, and net probable densities are calculated within each bounding box for the wiring required by each net for each edge respectively. The net probable densities are summed to produce total probable densities of wiring required by all of the nets for each edge respectively. The net probable density for each edge is calculated as being equal to a wiring capacity of the edge divided by the sum of the wiring capacity of the edge and all other unobscured edges within the bounding box that are collinear with the edge respectively.

Abstract: A DRAM memory array including a temperature sensor for adjusting a refresh rate depending upon temperature. The DRAM memory array includes a plurality of memory cells, each configured to allow storage and retrieval of more than two discrete memory states. A refresh circuit is coupled to the memory array for periodically refreshing the discrete storage state of each memory cell. The temperature sensor is situated on the same semiconductor die upon which the memory array is fabricated, and generates a signal indicative of the temperature of the semiconductor die. A control circuit receives the signal from the temperature sensor and responsively generates a refresh rate signal which is provided to control the refresh rate of the refresh circuit. In one specific implementation, a ROM look-up table is coupled to the control circuit and includes a plurality of entries which indicate the desired refresh rates for particular temperatures.

Abstract: An integrated circuit CPU is provided. The CPU has a program counter register; an instruction register; an instruction decoder connected directly to the instruction register; a register file responsive to control signals from the instruction decoder; an ALU operating upon data from the register file and generating results responsive to the control signals; and a result register that holds results while the results are written back to the register file. The CPU has only three pipelined stages of operation. The three stages comprise fetching an instruction from the memory subsystem into the instruction register; executing an instruction in the instruction register; and writing back results in the result register to the register file. Operating speeds are comparable to CPUs with a greater number of stages.

Abstract: Disclosed herein is a method and apparatus for compressing and decompressing audio and video signals. The audio and video signals can be compressed and decompressed according to different standards, such as MPEG-1 and MPEG-2. The audio and video signals can also be compressed and decompressed at different rates. Compression rates can be varied to fit the audio and video signals into a narrow transmission bandwidth, such as an RF transmission bandwidth.

Abstract: An inverse quantizer includes a multiplier circuit using two adder/subtracter stages to perform a multiplication operation between the quantizer scale value and the weight value. The inverse quantizer may be employed within a video decoder circuit such an an MPEG decoder. The multiplier circuit includes a control unit which receives the seven bit quantizer scale value. The control unit is configured to control a set of multiplexers which select either the weight value and/or bit shifted versions of the weight value to be operated upon by the two stage adder. Accordingly, each multiplexer circuit includes certain bit-shifted versions of the weight value as inputs. The control unit controls the multiplexer circuits such that appropriate inputs are channeled through the multiplexer circuits for operation by a pair of adder/subtracter circuits.

Abstract: In a physical design automation system for producing an optimized cell placement for an integrated circuit chip, a placement optimization methodology is decomposed into a plurality of cell placement optimization processes that are performed simultaneously by parallel processors on input data representing the chip. The results of the optimization processes are recomposed to produce an optimized cell placement. The fitness of the optimized cell placement is analyzed, and the parallel processors are controlled to selectively repeat performing the optimization processes for further optimizing the optimized cell placement if the fitness does not satisfy a predetermined criterion. The system can be applied to initial placement, routing, placement improvement and other problems. The processors can perform the same optimization process on different placements, or on areas of a single placement.

Abstract: A method for fabricating an electrically programmable memory device which has efficiency of electron injection from the channel to floating gate is provided. A substrate is provided having source and drain region with a channel therebetween. A floating gate structure is formed over portions of the source and drain regions and the channel. The structure includes a dielectric layer and a conductor layer thereover. The channel under the floating gate has both horizontal and vertical components. After forming the vertical and horizontal components, an N- drain region is formed in self-alignment with the vertical channel step region's edge. The depth of the N- drain is greater than the source region.

Abstract: A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).

Abstract: An electronic system having improved thermal transfer from a semiconductor die in a semiconductor device assembly (package) by at least partially filling a cavity in the package with a thermally conductive fluid, immersing a heat collecting portion of a heat pipe assembly into the fluid, and sealing the cavity. In order that the thermally conductive fluid does not chemically attack the die or its electrical connections, the die and connections can be completely covered with an encapsulating coating of an inorganic dielectric material, such as silicon dioxide, by any of a variety of techniques. The heat pipe provides highly efficient heat transfer from within the package to an external heat sink by means of an evaporation-condensation cooling cycle. The optional dielectric coating over the die permits selection of the thermally conductive fluid from a wider range of fluids by isolating the die and its electrical connections from direct contact with the fluid.

Abstract: A method (30) for interleaving a plurality of formatted data streams (10) on a network (20) wherein the formatted data streams (10) are divided into a further plurality of time bites (44) and synch characters (48) are added thereto in an add synch character operation (46). The time bites (44) are then transmitted as am assembled serial data stream (39) in a serializer (31). In a deserializer (32) the time bits (44) are reconstituted into the separate individual formatted data streams (10).

Abstract: A method of packaging an integrated circuit. An integrated circuit is connected to a substrate. A reservoir body is applied to the substrate, and the reservoir body and substrate define at least one reservoir and at least one flow gate. The reservoir body, substrate, and integrated circuit define a flow ring which extends at least partially around the circumference of the integrated circuit. A compound is dispensed into the reservoirs, and is flowed through the flow gates and into the flow ring, underfilling the integrated circuit.

Abstract: An open drain driver circuit includes first and second NMOS driver transistors, a delay circuit, an OR gate and an AND gate. Each NMOS driver transistor has a drain coupled to an output terminal, a source coupled to a supply terminal, and a gate. The delay circuit has an input coupled to the input terminal and has an output. The OR gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the first NMOS transistor. The AND gate has a first input coupled to the input terminal, a second input coupled to the output of the delay circuit and an output coupled to the gate of the second NMOS transistor.

Abstract: An MPEG decoder system and method an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes IDCT computation logic which computes the IDCT with improved performance. The IDCT logic performs the inverse DCT based on the Chen algorithm for IDCT computation. The system and method of the present invention efficiently utilizes properties of the coefficients in optimizing the matrix multiply functions, thus providing improved performance. Chen's algorithm is commonly used to perform the two-dimensional IDCT. According to the Chen algorithm, the transform matrix I is defined as:?I!=?Q!.times.?P!The Chen algorithm calculation can be written as:f=(Q.times.F.sup.T .times.Q.times.P).sup.T .times.PThe Q matrix is a diagonal matrix which has diagonal non-zero values, with the remainder of the values being 0. The P matrix includes a plurality of values which are the opposite sign of each other.

Abstract: A differential trellis decoding method for convolutional codes is provided which eliminates from candidacy half of the transitions in each round that it is used, thereby obviating the need for weight calculations for the eliminated transitions. The method is based on a decomposition of the code trellis into fully connected bipartite graphs and the observation that the symmetry of the bipartite graphs of the trellis permits the comparison and selection process for one state to influence the comparison and selection process for other states in the bipartite graph. This method results in a reduced number of operations and hence a reduced complexity for convolutional decoding.

Abstract: LDD regions of a MOSFET device in an integrated circuit structure are formed in a semiconductor substrate, after formation of the source/drain regions of the MOSFET device by forming spacers on the sidewalls of the gate electrode prior to doping of the substrate to form source/drain regions by implantation and annealing/activating. The sidewall spacers are then removed, and the portion of the substrate exposed by removal of the spacers is then lightly doped to form the desired LDD regions in the substrate between the respective source/drain regions and a channel region of the substrate below the gate oxide. In this manner, the dopant used to form the LDD regions is not exposed to the heat used to anneal and activate the implanted source/drain regions.