Patents Assigned to NEC Electronics
  • Patent number: 7853737
    Abstract: A communication data processing device according to an aspect of the invention includes a memory storing data, a data bus transmitting data read from the memory, a plurality of buffer memories temporarily storing data from the memory via the data bus and being capable of receiving and providing data independently of each other, a bus arbiter arbitrating use of the data bus to control data read from the memory to the plurality of buffer memories, an aligner aligning input data in a sequence corresponding to a packet communication, and a selector selecting a buffer memory from the plurality of buffer memories to output data from the selected buffer memory toward the aligner.
    Type: Grant
    Filed: May 5, 2005
    Date of Patent: December 14, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Daisuke Kawakami
  • Patent number: 7852157
    Abstract: A differential amplifier includes a differential amplifier section to generate a current composed of a differential-mode current and a first common-mode current according to a differential-mode component and a common-mode component of an input signal, a common-mode current generator section to generate a common-mode current according to the common-mode component of the input signal, and a current amplifier section to receive the current and the common-mode current, amplify a difference between the current and the common-mode current and output a result.
    Type: Grant
    Filed: February 25, 2009
    Date of Patent: December 14, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Tachio Yuasa
  • Patent number: 7853430
    Abstract: A semiconductor device includes a CDR (Clock Data Recovery) circuit and a frequency tracking control circuit. The CDR (Clock Data Recovery) circuit executes a clock data recovery on a serial data inputted synchronously with a spread spectrum clock. The frequency tracking control circuit controls a bandwidth of frequency which can be tracked by the CDR circuit.
    Type: Grant
    Filed: January 14, 2008
    Date of Patent: December 14, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Masao Nakadaira
  • Patent number: 7853798
    Abstract: A program tamper detecting apparatus includes an external memory, an activation ROM and a CPU. The external memory stores a first code for program tamper detecting and a first program, wherein the first program is encrypted. The activation ROM stores a second program for decrypting the first program. The CPU is electrically connected to the external memory and the activation ROM. The CPU decrypts the first program by executing the second program to obtain the decrypted first program. The CPU detects tampering of the first program based on a comparison between the first code and a result of a predetermined operation executed on second codes of the decrypted first program.
    Type: Grant
    Filed: February 4, 2005
    Date of Patent: December 14, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Takeshi Nakazawa
  • Publication number: 20100313053
    Abstract: A microcomputer system according to the present invention includes multiple backup power supplies that are used instead of the main power supply in response to a voltage drop of a main power supply. The microcomputer system further includes a backup power supply monitoring circuit that monitors charge amount of the multiple backup power supplies and determines whether the charge amount is lower than a predetermined charge amount, a backup power supply charging circuit that charges the backup power supply from the main power supply, where the backup power supply is determined by the backup power supply monitoring unit that the charge amount thereof is lower than the predetermined charge amount, and a power supply switching unit that switches to the backup power supply selected according to a predetermined rule if a voltage of the main power supply is reduced.
    Type: Application
    Filed: May 12, 2010
    Publication date: December 9, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Tomoaki Umezu
  • Publication number: 20100308874
    Abstract: A clock switch circuit includes a frequency divide circuit which divides a frequency of a basic clock to generate a plurality of frequency-divided clocks, an output select signal generation circuit which outputs an output select signal according to a clock select signal, and an output select circuit which switches a clock to be output according to the output select signal, in which the frequency divide circuit outputs a plurality of frequency-divided count values indicating the number of clocks of the basic clock from start of one cycle of each of the frequency-divided clocks, and the output select signal generation circuit switches a value of the output select signal at timings at which start timings of cycles of frequency-divided clocks before and after switch operation are matched based on a frequency-divided count value corresponding to a current selection clock among the plurality of frequency-divided count values.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 9, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Hiroshi SEKI, Kiyoshi Kirino
  • Publication number: 20100308867
    Abstract: A semiconductor device includes a first CPU, a second CPU having a configuration that is the same as or comparable to a configuration of the first CPU, and a comparator that compares an output of the first CPU with an output of the second CPU. The second CPU is made so as to have a lower operating margin than the first CPU. By supplying a same signal to the first CPU and the second CPU and then detecting a mismatch between the outputs of the first CPU and the second CPU as a result of comparison, the abnormality is predicted. The semiconductor device includes a reset control circuit that resets the device when the result of comparison by the comparator indicates an error.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 9, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Atsushi TAKAHASHI, Hiroyuki Kll
  • Publication number: 20100308387
    Abstract: A solid state imaging device having a light receiving region on a first surface side of a semiconductor substrate, incident light from an object to be imaged being illuminated on a second surface side of the semiconductor substrate, the solid state imaging device including an impurity diffusion layer formed on the first surface side of the semiconductor substrate, a surface of the impurity diffusion layer being silicided, and a gate electrode formed on the first surface side of the semiconductor substrate. The impurity diffusion layer includes the light receiving region disposed on the first surface side of the semiconductor substrate, a surface of the light receiving region being silicided, and the impurity diffusion layer includes at least a surface adjacent to the gate electrode.
    Type: Application
    Filed: August 16, 2010
    Publication date: December 9, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Hiroaki Ohkubo, Yasutaka Nakashiba
  • Publication number: 20100312940
    Abstract: A DMA transfer control device comprises: a DMA arbiter that performs DMA transfer for each DMA channel formed by a combination of a memory and a plurality of input/output devices and DMA controller circuits that control the DMA arbiter; a judgment unit and a transfer time calculation unit that calculates a next DMA transfer scheduled time based on the DMA transfer size for a DMA transfer request and a judgment time. A timer counter that times the judgment time at a unit time interval, and a comparator that compares the judgment time at which a DMA transfer request arrives with the DMA transfer scheduled time are also provided, and the judgment unit sends the DMA transfer permission to the DMA arbiter when an output of the comparator indicates that the judgment time is not earlier than the DMA transfer scheduled time. The efficiency of data transfer by dynamically controlling DMA transfer is performed.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 9, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Naoko SHINOHARA
  • Publication number: 20100308667
    Abstract: A semiconductor device is provided with a first power supply cell, first cells and second cells. The first power supply cell and the first cells are continuously arrayed in a row direction in a first row. The second cells are continuously arrayed in the row direction in a second row adjacent to the first row. The first power supply cell is connected to a first power supply line extending perpendicularly to the row direction to feed a power supply voltage corresponding to a voltage fed from the first power supply line to the plurality of first and second cells. One of the second cells is indirectly connected to the first power supply line through the first power supply cell, the one of the second cells being positioned adjacent to the first power supply cell.
    Type: Application
    Filed: May 28, 2010
    Publication date: December 9, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Taro Sakurabayashi
  • Patent number: 7849295
    Abstract: A data processing apparatus includes an operation processing unit and a data feature determining circuit. The operation processing unit is configured to sequentially perform preset operation processing on operation data in units of sub blocks to output an operation resultant data. Each of the operation data is divided into blocks, each of which comprises the sub blocks. The data feature determining circuit is configured to control the operation processing unit in units of blocks based on feature data respectively added to the blocks to indicate features of the blocks.
    Type: Grant
    Filed: June 15, 2007
    Date of Patent: December 7, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hideki Sugimoto
  • Patent number: 7847585
    Abstract: A semiconductor integrated circuit device comprises a transistor circuit exhibiting inductance at a desired frequency owing to capacitance between electrodes in a MOS transistor, the transistor circuit having an impedance that increases with an increase in frequency; and a first MOS transistor that functions as a source follower having the transistor circuit as a load.
    Type: Grant
    Filed: May 14, 2009
    Date of Patent: December 7, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Kanji Takeda
  • Patent number: 7846830
    Abstract: The objects of the present invention is to improve the impact resistance of the semiconductor device against the impact from the top surface direction, to improve the corrosion resistance of the surface of the top layer interconnect, to inhibit the crack occurred in the upper layer of the interconnect layer when the surface of the electrode pad is poked with the probe during the non-defective/defective screening, and to prevent the corrosion of the interconnect layer when the surface of electrode pad is poked with the probe during the non-defective/defective screening. A Ti film 116, a TiN film 115 and a pad metal film 117 are formed in this sequence on the upper surface of a Cu interconnect 112. The thermal annealing process is conducted within an inert gas atmosphere to form a Ti—Cu layer 113, and thereafter a polyimide film 118 is formed, and then a cover through hole is provided thereon to expose the surface of the pad metal film 117, and finally a solder ball 120 is joined thereto.
    Type: Grant
    Filed: October 12, 2007
    Date of Patent: December 7, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Toshiyuki Takewaki, Noriaki Oda, Yorinobu Kunimune
  • Publication number: 20100302694
    Abstract: It is desired to achieve a high ESD protection performance by a small area circuit. An electrostatic discharge protection circuit includes: protection circuits, wherein each protection circuit includes a MOS transistor; and a trigger circuit configured to supply a trigger signal to a gate electrode of the MOS transistor of each protection circuit in response to a surge voltage between a low potential node and a high potential node. Each protection circuit is configured to electrically connect the low potential node and the high potential node to one another when the trigger signal is supplied to the gate electrode. The gate electrode of each protection circuit is connected to a resistive element having larger resistance value than Rmax, supposing that Rmax is a largest parasitic resistance between each of the plurality of protection circuit and an output of the trigger circuit.
    Type: Application
    Filed: May 21, 2010
    Publication date: December 2, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Yasuyuki Morishita
  • Publication number: 20100301910
    Abstract: A frequency synthesizer comprises a VCO group; a phase comparator; and a loop filter. Each VCO includes a varactor and a capacitor bank including a plurality of weighted capacitance elements, and a plurality of switches turned ON and OFF based on a control signal. Also provided a temperature compensation including a varactor correction potential generation circuit, a correction potential generation circuit for parasitic capacitance of the capacitor bank, a variable gain amplifier in which weighting processing, based on a control signal of the capacitor bank, is performed on an output potential of the correction potential generation circuit, and an adder circuit that adds the output voltage of the correction potential generation circuit of the varactor and output voltage of the variable gain amplifier, and the varactor of the VCO is controlled by output (correction potential) of the adder circuit.
    Type: Application
    Filed: May 18, 2010
    Publication date: December 2, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Weiliang Hu, Noriaki Matsuno
  • Publication number: 20100306727
    Abstract: A layout region in which a wiring pattern and a special pattern are placed is divided into division regions. The minimum pitch for the special pattern is larger than the minimum pitch for the wiring pattern. With respect to each division region, the special pattern included in a predetermined region surrounding the each division region is extracted as a peripheral pattern, and a dummy pattern placement region included in the each division region is determined. The dummy pattern placement region is apart from at least one of boundaries between adjacent division regions. A dummy pattern is added in the dummy pattern placement region with avoiding a design rule error with the peripheral pattern existing around the each division region. Then, the plurality of division regions to which the dummy pattern is added are coupled with each other.
    Type: Application
    Filed: May 24, 2010
    Publication date: December 2, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Daishin Itagaki
  • Publication number: 20100301956
    Abstract: A voltage-controlled oscillator includes a resonator section in which a plurality of types of variable capacitance elements having different structures and capacitance variation characteristics are connected in parallel and capacitance values of the plurality of types of variable capacitance elements are controlled simultaneously by a control voltage; and an amplifier section for maintaining oscillation produced by the resonator section. Varactor diodes and MOS varactors can be used as the variable capacitance elements.
    Type: Application
    Filed: May 21, 2010
    Publication date: December 2, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Yoshiaki NAKAMURA
  • Publication number: 20100301488
    Abstract: In a semiconductor device, a lower multi-layered interconnect structure, an intermediate via-level insulating interlayer, and an upper multi-layered interconnect structure are stacked in this order in a region overlapped with a bonding pad in a plan view; upper interconnects and vias of the upper multi-layered interconnect structure are formed so as to be connected to the bonding pad in the pad placement region; the intermediate via-level insulating interlayer has no electro-conductive material layer, which connect the interconnects or vias in the upper multi-layered interconnect structure with interconnects or vias in the lower multi-layered interconnect structure, formed therein; and the ratio of area occupied by the vias in the via-level insulating interlayers contained in the lower multi-layered interconnect structure is smaller than the ratio of area occupied by the vias in the via-level insulating interlayers contained in the upper multi-layered interconnect structure.
    Type: Application
    Filed: May 4, 2010
    Publication date: December 2, 2010
    Applicant: NEC Electronics Corporation
    Inventors: Noriaki Oda, Shinichi Chikaki
  • Publication number: 20100302699
    Abstract: An electrical fuse circuit is provided with: a protection element having a first terminal connected to a power source and outputting a fusing voltage from a second terminal; an electrical fuse having a third terminal connected to the second terminal of the protection circuit; and a fusing transistor connected between the electrical fuse and ground to switch a current through the electrical fuse. The second terminal of the protection element is connected to a gate of the fusing transistor.
    Type: Application
    Filed: May 21, 2010
    Publication date: December 2, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Masayuki Minami
  • Publication number: 20100301895
    Abstract: Provided is a test system of a semiconductor integrated circuit including an output device and an input device for conducting an input/output characteristics test of the output device and the input device inside the semiconductor integrated circuit. In the system, a transmission line provided in a test board where the semiconductor integrated circuit is mounted on establishes a wired connection between an external terminal of one circuit of one of the output device and the input device and external terminals of a plurality of circuits of another one of the output device and the input device.
    Type: Application
    Filed: May 27, 2010
    Publication date: December 2, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Shinsuke Hamanaka