Abstract: An image decoding apparatus includes an analyzing section and an image decoding section. The analyzing section determines a process quantity of a coded image data to each of a plurality of image decoding processes within a unit process time based on a parameter of the coded image data, prior to the plurality of image decoding processes. The image decoding section carries out each of the plurality of image decoding processes to the coded image data for the determined process quantity such that a decoded image data is generated from the coded image data.

Abstract: A display control device has: a shift register generating n shift pulses in series; a data hold block configured to hold n gradation data; and a DA converter for converting the n gradation data into corresponding gradation voltages. The data hold block includes: n first latch circuits configured to respectively latch the n gradation data in series in synchronization with the n shift pulses; and n second latch circuits provided between the DA converter and the n first latch circuits. An electrical connection between the first latch circuits and the second latch circuits is cut off while the first latch circuits receive the n gradation data. After the first latch circuits finish latching all the gradation data, the n gradation data are simultaneously supplied to the DA converter from the first latch circuits through the second latch circuits.

Abstract: To provide a disk reproducing apparatus capable of reading data at a lower error rate without requiring a complicated circuit configuration. An embodiment of the present invention provides a disk reproducing apparatus for reproducing a data signal based on a signal read from a disk and having a clock cycle that is an integral multiple of a cycle of a reproduction clock, including: a clock generating unit generating the reproduction clock based on an input signal obtained by binarizing the signal read from the disk; an error component detecting unit detecting an error component in the input signal; a threshold storage unit storing a threshold value for determining the error component; and a data signal reproducing unit reproducing the data signal in the input signal based on the error component detected by the error component detecting unit and the threshold value stored in the threshold storage unit.

Abstract: In a semiconductor device, a semiconductor substrate is sectioned into a logic-circuit formation section in which a plurality of logic circuits are formed, and a memory formation section in which a plurality of memory cells are formed. A multi-layered insulating layer is formed on the substrate, and a conductive structure is formed in the insulating layer at the logic-circuit formation section. Capacitors are formed in the insulating layer at the memory formation section. Each of the capacitors includes a lower capacitor electrode, a capacitor dielectric layer formed on the lower capacitor electrode, and an upper capacitor electrode formed on the capacitor dielectric layer, with upper is end faces of the upper capacitor electrodes being coplanar with an upper end face of the conductive structure. Bit-line layers are formed in the insulating layer below the lower capacitor electrodes at the memory formation section.

Abstract: A driver of a display device has an output buffer, a frame control circuit outputting a frame switch signal with respect to each frame, and an offset compensation control circuit outputting an offset compensation control signal to the output buffer in response to the frame switch signal. One frame includes a display period and a non-display period. In normal processing, the frame control circuit receives a first vertical synchronizing in one frame and outputs the frame switch signal from the receipt of the first vertical synchronizing signal to before the non-display period within the same frame. In special processing, the frame control circuit further receives a second vertical synchronizing signal in the non-display period in one frame, and further outputs the frame switch signal for a time from the receipt of the second vertical synchronizing signal to before the non-display period in the next frame.

Abstract: A controlling unit disposed in a PLL circuit controls a phase interpolator to gradually change a phase shift amount applied to a phase shift signal C_PS by a unit of basic delay amount ? at a timing predetermined in accordance with a modulation profile of an SSC. Further, the controlling unit controls a total phase shift amount applied to the phase shift signal C_PS output from the phase interpolator in one period of a feedback clock signal C_FB obtained by dividing frequency of the phase shift signal C_PS in a way that a difference between the total phase shift amount and a total phase shift amount in a previous one period of C_FB is always equal to or less than the basic delay amount ?.

Abstract: A semiconductor device includes a MOSFET cell having a super junction structure and a diode cell connected in parallel with the MOSFET cell and having the same plan shape as the MOSFET cell. The MOSFET cell includes an epitaxial layer of a first conductivity type formed on a semiconductor substrate, a gate electrode and a first column region of a second conductivity type formed in the epitaxial layer, a first base region of the second conductivity type formed on a surface of the epitaxial layer, and a source region of the first conductivity type formed on a surface of the first base region. The diode cell includes a second column region of the second conductivity type formed in the epitaxial layer and having a larger width than the first column region, and a second base region of the second conductivity type formed on the surface of the epitaxial layer.

Abstract: There is provided a wireless communication system capable of requesting activation from a host without reserving a time slot for performing data transfer. There is provided a wireless communication system provided with a host 1 and devices (2-1) to (2-n) which perform wireless communication with the host 1. The devices (2-1) to (2-n) transmit a remote activation notification requesting activation of the host 1 during a beacon period which is a period for reserving a time slot for performing data transfer. When receiving the remote activation notification from the devices (2-1) to (2-n), the host 1 returns from a sleep state to an active state.

Abstract: A display device includes a display portion; a signal driver; and a delay control circuit. The display portion is connected to a plurality of signal line groups. The signal driver is connected to the plurality of signal line groups and outputs a plurality of video data groups to the plurality of signal line groups at timings respectively in a single horizontal period. Each of the timings is shifted from an adjacent timing by a predetermined time. The delay control circuit varies the predetermined time every horizontal period and supplies the predetermined time to the signal driver.

Abstract: A video signal processing apparatus generates first to third correlation values based on five sequential video line signals C(n?2) to C(n+2) that include two kinds of color-difference signals transmitted line sequentially. The first correlation value indicates degree of similarity between C(n+1) and C(n?1), the second correlation value indicates degree of similarity between C(n+2) and C(n), and the third correlation value indicates degree of similarity between C(n) and C(n?2). When the degree of similarity between C(n+1) and C(n?1) is evaluated to be smaller than a predetermined level based on the first correlation value, the apparatus determines a mixing ratio of C(n+1) and C(n?1) according to relative magnitude of the third correlation value with respect to the second correlation value. The apparatus outputs a mixed signal obtained by mixing the signals C(n+1) and C(n?1) according to the mixing ratio and the video signal C(n) as two simultaneous color-difference signals.

Abstract: A semiconductor device 1 is a semiconductor device of the BGA type, and includes a semiconductor chip 10, a resin layer 20, an insulating layer 30, and an external electrode pad 40. The resin layer 20 is constituted by a sealing resin 22 and an underfill resin 24, and covers the semiconductor chip 10. The insulating layer 30 is formed on the resin layer 20. The external electrode pad 40 is formed in the insulating layer 30. This external electrode pad 40 extends through the insulating layer 30. One surface S1 of the external electrode pad 40 is exposed in the surface of the insulating layer 30, and the other surface S2 is located in the resin layer 20. A concave portion 45 is formed in the surface S2 of the external electrode pad 40. The resin composing the resin layer 20 enters into the concave portion 45.

Abstract: A semiconductor light receiving device includes a plurality of photodiode units, each of which is configured to convert a received light into an electric signal; and a separating unit configured to electrically separates the plurality of photodiode units from each other. The impurity concentration of a surface portion of the separating unit is equal to or lower than a first concentration. The first concentration is a concentration at which the light receiving sensitivity of the separating unit to light is substantially equal to the light receiving sensitivity of each of the plurality of photodiode units of the light. A wavelength of the light is equal to or longer than that of blue-violet light.

Abstract: A drive circuit that is an example of the present invention is a drive circuit of a display device for outputting in parallel the analog picture signals generated based on the digital picture signals inputted in serial. This circuit comprises a level shift circuit for converting the voltage level of the digital picture signals that were inputted in serial, a D/A conversion circuit for generating analog picture signals based on the digital picture signals that were subjected to level conversion with the level shift circuit, and an expansion circuit connected to the output side of the D/A conversion circuit or between the level shift circuit and the D/A conversion circuit and serving to expand and hold the inputted serial picture signals in parallel and output the picture signals in parallel. The level shift circuit is thus formed in the front stage of the picture signal register circuit.

Abstract: A data transfer control device, which transfers a large capacity of data speedily and sequentially, has three buffers that are used as a WR (write) buffer, an intermediate buffer, and an RD (read) buffer. To send data sequentially, the data transfer control device switches-over the buffers in one of the following three ways (A), (B), and (C), using determination flags indicating whether the buffers store effective data (data not yet referenced). A buffer control device switches-over (A) the WR buffer and RD buffer if a WR buffer effective flag 33 is on and an intermediate buffer effective flag 34 and an RD buffer effective flag 35 are off, (B) the WR buffer and the intermediate buffer if the WR buffer effective flag 33 and the RD buffer effective flag 35 are on and the intermediate buffer effective flag 34 is off, and (C) the intermediate buffer and the RD buffer if the intermediate buffer effective flag 34 is on and the RD buffer effective flag 35 is off.

Abstract: A leadless type resin-sealed semiconductor package includes a resin enveloper having a mounting face to be applied to a wiring board, and at least one side face associated with the mounting face to produce an angled side edge. A semiconductor chip is encapsulated and sealed in the resin enveloper. An electrode terminal is partially buried in the angled side edge of the resin enveloper so as to be exposed to an outside, with the electrode terminal being electrically connected to the semiconductor chip. The electrode terminal is formed with a depression which is shaped so as to be opened to an outside when the resin enveloper is placed on the wiring board such that the mounting face of the resin enveloper is applied thereto.

Abstract: A drive circuit that is an example of the present invention is a drive circuit of a display device for outputting in parallel the analog picture signals generated based on the digital picture signals inputted in serial. This circuit comprises a level shift circuit for converting the voltage level of the digital picture signals that were inputted in serial, a D/A conversion circuit for generating analog picture signals based on the digital picture signals that were subjected to level conversion with the level shift circuit, and an expansion circuit connected to the output side of the D/A conversion circuit or between the level shift circuit and the D/A conversion circuit and serving to expand and hold the inputted serial picture signals in parallel and output the picture signals in parallel. The level shift circuit is thus formed in the front stage of the picture signal register circuit.

Abstract: A positioning apparatus having short sensory time for executing the high precision positioning of the user on a map. The positioning apparatus includes: a first positioning unit for obtaining a first position information which represents the position of the positioning apparatus itself measured by carrying out a low precision positioning; a displaying unit for displaying the first position information; and a second positioning unit for obtaining the second position information which represents the position of the positioning apparatus itself measured by carrying out a high precision positioning. The high precision positioning is executed in parallel with the low precision positioning. The displaying unit updates a screen based on the second position information.

Abstract: A clock generator circuit provides an output clock without an abnormal waveform pulse which causes faulty operation in other function circuits. A phase synchronizing circuit outputs a second clock synchronized with a first clock. A selector signal generator circuit outputs a switching signal when detecting the abnormal waveform pulse in the second clock. A selector outputs the first clock instead of the second clock as the output clock based on the switching signal. A delay circuit delays the second clock input to the selector so that the selector switches the output clock from the second clock to the first clock before the abnormal waveform pulse is input to the selector.

Abstract: A method of analyzing of a semiconductor integrated circuit includes inspecting a physical defect in a semiconductor wafer, subjecting the semiconductor integrated circuit chip to a logic test and extracting a malfunctioning chip, analyzing a detected signal observed from the malfunctioning chip by an analyzer, obtaining the layer and coordinates of a circuit related the detected signal, collating the physical defect with the circuit, and identifying the physical defect associated with the circuit. The layer and coordinates of the circuit is extracted using design data. An inspection step identifying information is collated with the layer of the circuit, and an in-chip coordinates of the physical defect is collated with the coordinated of the circuit.

Abstract: A tilt inspection apparatus which detects tilt of an object to be observed with respect to a placement surface on which the object is placed, including: a light source which irradiates light or projects an image onto the object to be observed; a light shield plate which has a first slit extended in a first direction and a second slit extended in a second direction normal to the first direction, and is disposed between the light source and the object to be observed; and a carriage mechanism which supports the light shield plate so as to be rotatable in the in-plane direction of the light shield plate, and fixes the light shield plate while aligning the first slit normal to the placement surface is provided.