Abstract: Provided is a memory system that can specify a cause of an error. According to the memory system, during writing, when write data is looped back, and the write data is an error, the error has occurred between first processing units (51 to 53) or second processing units (56 to 58) and an input/output unit (60). Thus, whether the error has occurred between the first processing units (51 to 53) or the second processing units (56 to 58) and the input/output unit (60), or in a memory (8) can be specified.

Abstract: A cutting machine including a die, and a cutting punch having a cutting edge, and configured to bring the cutting punch close to the die to have the cutting edge face to a surface of the die thereby cut a work, the cutting punch being provided with a local slope, wherein the cutting machine is configured, using a light source, to irradiate a light such that the light transmit through the clearance between the cutting punch and the surface of the die and to reflect on the local slope such that the direction of the path of the light is changed so as to yield reflected light to be observed is provided.

Abstract: A semiconductor device is composed of a first circuit receiving a first power supply voltage; and a second circuit receiving a second power supply voltage. The second power supply voltage is higher than the first power supply voltage. Such device arrangement is effective for reducing the soft error rate, when the second circuit is more susceptive to a soft error than the first circuit, especially when the second circuit is a memory device.

Abstract: Disclosed is a semiconductor memory device having memory cells that are in need of refresh for data retention, includes control circuits for necessarily generating the refresh immediately before the read/write operation, and for setting the latency to a first fixed value at all times, for the first mode during the testing, and for necessarily generating the refresh immediately after the read/write operation, and for setting the latency to a second fixed value at all times, for the second mode during the testing.

Abstract: Provided are: a method of manufacturing semiconductor device which has multilayer interconnection in a damascene structure and a conductive barrier film such as CoWP film, and which has more excellent electric characteristics than a conventional one. To this end, when a via hole reaching a lower wiring is formed, a reaction layer formed between a conductive barrier film and the lower wiring and remaining on the surface of the lower wiring is removed. Thus, at an interface where a lower surface of the via and the lower wiring are joined, the reaction layer, formed between the conductive barrier film and the lower wiring, does not exist, so that the via resistance can be sufficiently reduced.

Abstract: A first electronic circuit component and a second electronic circuit component are electrically connected to an electro-conductive member via a first solder and a second solder, respectively. The electro-conductive member is formed in a resin film. The electro-conductive member is configured as containing a second diffusion barrier metal film. The second diffusion barrier metal film prevents diffusion of the second solder. Between the electro-conductive member and the first solder, a first diffusion barrier metal film is provided. The first diffusion barrier metal film prevents diffusion of the first solder. On the first surface of the resin film and on the electro-conductive member, an adhesive metal film is formed so as to contact with the resin film and the electro-conductive member. The adhesive metal film has stronger adhesiveness to the resin film than either of those of the first solder and the first diffusion barrier metal film.

Abstract: A complementary signal generating circuit according to an embodiment of the present invention includes: an inverting element inverting a first signal to generate a second signal; a first transistor connecting a first power supply potential and a first output terminal electrically in accordance with the first signal; a second transistor connecting the first output terminal and a second power supply potential electrically in accordance with the second signal; a third transistor connecting the first power supply potential and a second output terminal electrically in accordance with the second signal; and a fourth transistor connecting the second output terminal and the second power supply potential electrically in accordance with the first signal.

Abstract: An audio processor chip includes a DSP for decoding audio data, a first DAC for performing a D/A conversion to the digital data obtained from the DSP, a PLL circuit for generating a clock signal for the first DAC to supply it to the first DAC and a clock output external terminal for outputting the clock signal obtained from the PLL circuit to a second DAC of an AFE. The first DAC 142 outputs an analog signal obtained from the D/A conversion to an analog mixer and the analog mixer performs a mixing process to the analog signal to output.

Abstract: Aiming at providing a semiconductor device advanced in performance of transistors, and improved in reliability, a semiconductor device of the present invention has a semiconductor element, a frame component provided over the semiconductor element, while forming a cavity therein, and a molding resin layer covering around the frame component, wherein the frame component is composed of a plurality of resin films (a first resin film and a second resin film) containing the same resin, and the cavity allows the active region of the semiconductor element to expose therein.

Abstract: A semiconductor device that can suppress noise transmission through a seal ring provided between two device regions. The semiconductor device includes a logic unit and an analog unit. The semiconductor device further includes a silicon substrate, an insulating interlayer, a seal ring surrounding the outer periphery of the logic unit composed of a conductive film buried in the insulating interlayer, a well provided on the silicon substrate, and an N well guard ring that blocks conduction of a path from the logic unit, through the seal ring to the analog unit. The N well guard ring is disposed between the seal ring region 106 and the logic unit or the analog unit.

Abstract: To provide a semiconductor device capable of reducing a gate capacitance, and preventing breakdown of a gate oxide film if a large amount of current flows. A semiconductor device according to an embodiment of the present invention includes: an epitaxial layer; a channel region formed on the epitaxial layer; a trench extending from a surface of the channel region to the epitaxial layer; a gate oxide film that covers an inner surface of the trench; a gate electrode filled into the trench; and a buried insulating film formed below the gate electrode and away from the gate oxide film.

Abstract: A semiconductor device according to an embodiment of the present invention includes: a plurality of clock domains including a plurality of logic circuits operating in accordance with a clock signal; and a control circuit selectively supplying the clock signal to a predetermined number of clock domains selected from the plurality of clock domains based on a control signal.

Abstract: In a communication system based on OSI (Open Systems Interconnection) Reference Model, a pattern body generation circuit of a transmitting device generates and outputs a jitter test pattern body for jitter test. A selector selects an output (frame data) of a transmitting-end upper circuit during normal communication and selects an output (pattern body) of the pattern body generation circuit during jitter test. A transmitting-end MAC circuit performs transmitting-end processing of a MAC layer on the data selected by the selector to thereby obtain a MAC frame. A receiving-end MAC circuit performs receiving-end processing of a MAC layer on a received frame in MAC frame format to thereby obtain a payload. A pattern body verification circuit verifies a pattern body that is a payload obtained by the receiving-end MAC circuit during jitter test against a corresponding pattern body before transmission.

Abstract: A semiconductor memory device that does not delay read/write access due to a refresh and can be interface compatible with a high-speed SRAM such as a QDR SRAM, comprises a plurality of subarrays each having a plurality of dynamic memory cells; at least one cache memory for the plurality of subarrays; a circuit to check whether data read from the subarray selected by a read address is present in the cache memory or not; and a circuit performing control so that the check result indicates that the data is present in the cache memory, the data is read from the cache memory and refreshing of the subarray is performed concurrently with a read cycle.

Abstract: A solid state imaging device includes: a light receiving portion; a transfer gate; a clock wiring group; and a substance. The light receiving portion includes a plurality of light receiving elements formed on a substrate. The charge transfer portion transfers electric charges supplied from the light receiving portion. The transfer gate is provided between the light receiving portion and the charge transfer portion and supplies the electric charges accumulated in the light receiving portion to the charge transfer portion. The clock wiring group includes a plurality of wirings and supplies a plurality of clocks for transferring the electric charges. The substance shields light with a wavelength lower than a predetermined wavelength. The plurality of wirings is arranged away from one another with a gap corresponding to the predetermined wavelength. The substance is arranged to cover the gap and shields light with a wavelength possibly passing through the gap.

Abstract: Disclosed is a logic circuit which includes first and second MOS transistors which are connected in series between a first signal-input terminal and GND. The gates of the first and second MOS transistors are connected in common to a second signal-input terminal and a connection node between the drains of the first and second MOS transistors is connected to an output terminal. When the first and second MOS transistors are both in an off state, the output terminal is less than or equal to a low level.

Abstract: An array-type computer processor including a data path unit communicating with a state control unit obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes comprising cooperative partial instruction codes corresponding to contexts and operation states for the data path unit and the state control unit, respectively, from an external program memory which stores data of a computer program.

Abstract: A wiring substrate includes a base insulating film, a first interconnection formed on a top surface side of the base insulating film, a via conductor provided in a via formed in the base insulating film, and a second interconnection provided on a bottom surface side of the base insulating film. The second interconnection is connected to the first interconnection via the via. The wiring substrate includes divided-substrate-unit regions, in each of which the first interconnection, the via, and the second interconnection are formed. The wiring substrate includes a warpage-controlling pattern on the base insulating film, with a warped shape such that when the wiring substrate rests on a horizontal plate, at least a central part of a plane surface of the substrate contacts the horizontal plate, with both ends of the side raised.

Abstract: There is provided a variable-gain amplifier, including two cascode amplifiers and an attenuator. The cascode amplifiers are mutually connected in parallel via the attenuator.

Abstract: A semiconductor device 1 includes a substrate 10, a semiconductor chip 20 (first semiconductor chip), semiconductor chips 30 (second semiconductor chips) and a heat sink 40. Semiconductor chips 20 and 30 are mounted on the substrate 10. The level of the top surface of the semiconductor chip 20 on the substrate 10 is lower than the level of the top surface of the semiconductor chip 30. A heat sink 40 is fixed to the semiconductor chip 20. Among the semiconductor chip 20 and the semiconductor chips 30, only above the semiconductor chip 20 is provided with the heat sink 40.