Abstract: A semiconductor device 1 includes a substrate 10, a semiconductor chip 20 (first semiconductor chip), semiconductor chips 30 (second semiconductor chips) and a heat sink 40. Semiconductor chips 20 and 30 are mounted on the substrate 10. The level of the top surface of the semiconductor chip 20 on the substrate 10 is lower than the level of the top surface of the semiconductor chip 30. A heat sink 40 is fixed to the semiconductor chip 20. Among the semiconductor chip 20 and the semiconductor chips 30, only above the semiconductor chip 20 is provided with the heat sink 40.

Abstract: An n-type drift region includes an active element region and a peripheral region. A p-type base region is formed at least in the active element region. A trench-type gate electrode is formed in each of the active element region and the peripheral region. An n-type source region formed in the base region. A plurality of p-type column regions is selectively formed separately from one another in each of the active element region and the peripheral region. In a peripheral region, a p-type guard region is formed below the gate electrode. In the active element region, the p-type guard region is not formed below the gate electrode. As a result, it is possible to hold the breakdown voltage in the peripheral region at a higher level than in the active element region while maintaining the low ON resistance due to a superjunction structure and to raise the breakdown voltage performance of the semiconductor device.

Abstract: A semiconductor device contains a semiconductor substrate having a p-type semiconductor layer and an n-type channel layer formed thereon; gate trenches extended through the channel layer so as to reach the p-type semiconductor layer; oxide films formed over the bottom and inner wall of the gate trenches, the oxide films being formed thicker over the bottom of the gate trenches than over the inner wall; gate electrodes formed so as to fill the gate trenches; n-type regions formed at the bottom of the gate trenches, and containing arsenic as a major n-type impurity component; low concentration p-type regions formed under the n-type regions, and having a low p-type impurity concentration; and a drain electrode formed on the back surface of the substrate.

Abstract: A cache memory device includes an address generation unit, a data memory, a tag memory, and a hit judging unit. The address generation unit generates a prefetch index address included in a prefetch address based on an input address supplied from a higher-level device. The tag memory stores a plurality of tag addresses corresponding to a plurality of line data stored in the data memory. Further, the tag memory comprises a memory component that is configured to receive the prefetch index address and an input index address included in the input address in parallel and to output a first tag address in accordance with the input index address and a second tag address in accordance with the prefetch index address in parallel. The hit judging unit performs cache hit judgment of the input address and the prefetch address based on the first tag address and the second tag address.

Abstract: A semiconductor device, including: a first transistor formed on a substrate and including an Hf contained film as its gate insulating film; and a second transistor formed on said substrate and having the same conductive type as that of said first transistor, said second transistor including a silicon oxide film and not including an Hf contained film as its gate insulating film is provided.

Abstract: An adapter board includes a package substrate having a first surface and a second surface and further including a board having wirings formed therein, pads disposed in the device side, and the pads disposed in the bump side, an insulating resin layer joined to the first surface, through holes formed in the positions corresponding to the pads in the insulating resin layer, vias formed in the through holes, and pads covering the through holes, wherein the pads are electrically coupled to the pads through the wirings, and the pads are electrically coupled to the pads through the vias.

Abstract: A differential amplifier circuit is provided with a first input stage including a transistor pair of a first conductivity type, of which transistor pair receives differential input signals; a first output stage connected to the first input stage; a second input stage including a transistor pair of a second conductivity type different from the first conductivity type, of which transistor pair receives the differential input signals; a second output stage connected to the second input stage; and an output terminal.

Abstract: A dynamic type semiconductor memory device includes a sense amplifier connected with a bit line pair to amplify and sense a voltage difference on the bit line pair; a precharge circuit configured to precharge the bit line pair to a power supply voltage on a lower side in response to a first control signal; a memory cell capacitance having one end which is connected with the bit line pair through a first switch circuit which is controlled in response to a signal on a word line; and a reference cell capacitance having one end which is connected with the bit line pair through a second switch circuit which is controlled in response to a signal on a reference word line. The other end of the memory cell capacitance and the other end of the reference cell capacitance are electrically separated.

Abstract: A semiconductor integrated circuit has: a substrate; a basic logic cell placed on the substrate and configured to function as a part of a logic circuit; and a dummy cell placed on the substrate and not configured to function as a part of a logic circuit. The basic logic cell includes a diffusion layer formed in the substrate, and a distance from the diffusion layer to a boundary between the basic logic cell and another cell adjacent to the basic logic cell is equal to a first distance. The dummy cell includes a dummy diffusion layer that is a diffusion layer formed in the substrate, and a distance from the dummy diffusion layer to a boundary between the dummy cell and another cell adjacent to the dummy cell is equal to the first distance.

Abstract: Provided is a semiconductor integrated circuit including: a first path that includes a first logic circuit; a second path that includes a second logic circuit; and a subsequent-stage circuit that is connected to an output of the first path and is connected to an output of the second path, in which the second path further includes a first internal path that is selected as a propagation path during a normal operation period; and a second internal path that is selected as a propagation path during a test operation period and includes a delay circuit having a delay amount larger than a delay amount of the first internal path.

Abstract: To facilitate counting of memory cells in failure analysis, without limiting the arrangement of memory cells or increasing the number of processes. A memory cell array region 3 in which memory cells 3a are formed in a repetitive pattern is formed on a semiconductor substrate 2. Power supply wirings 4a and ground wirings 4b in a predetermined layer formed on the memory cell array region 3 are vertically and horizontally arranged in the form of a gird to correspond to the arrangement of the memory cells 3a at least in the memory cell array region 3.

Abstract: A method for manufacturing a semiconductor device includes preparing two substrates having a first and a second surface and having first and second pads and a second testing-dedicated pad, the first pads in the first surface, the second pads in the second surface and arranged with an inter-pad distance that is larger than that for the first pad, and the second testing-dedicated pad being in the second surface; coupling a wafer with a apparatus, and inspecting the wafer with a probe card, the wafer having a LSI, which is an object of an inspection, the apparatus applicable signal to the LSI formed in the wafer, and measurable electrical characteristics of the LSI formed in the wafer, and the probe card having one of the two substrates; dicing the wafer into semiconductor elements containing the LSI; and packaging the semiconductor element over the other of the two substrates.

Abstract: Provided is a wiring substrate which enables wiring density to be increased and enables transmission speed of signals to be adjusted without making a design change of wirings. A wiring substrate 100 is provided with a first terminal 110, a second terminal 120, a first wiring 112 and a second wiring 114. The first wiring 112 is such that one end thereof is connected to the first terminal 110, and is formed on the wiring substrate 100. The second wiring 114 is such that one end thereof is connected to the second terminal 120, and is formed on the wiring substrate 100. One end of each of a plurality of third wirings formed on the wiring substrate 100 is connected to the other end of the first wiring 112, and one end of each of a plurality of fourth wirings formed on the wiring substrate 100 is connected to the other end of the second wiring 114. The other end of at least one third wiring and the other end of at least fourth wiring are connected together.

Abstract: A semiconductor device, includes: a semiconductor substrate; a multilayered interconnect structure formed on the semiconductor substrate; a terminal for flip-chip packaging arranged on the surface of the multilayered interconnect structure; and a spiral inductor formed to enclose the terminal for flip-chip packaging, in a plan view, which is not electrically connected with the spiral inductor. The spiral inductor may be provided for peaking by which the gain reduction caused in a high frequency is compensated.

Abstract: A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.

Abstract: A pipeline type analog-digital converter includes a first to an N-th (N is an integer of not less than 2) stages (101 to 10N) brought into cascade connection and converting an analog signal input from a preceding stage to a digital signal of a predetermined bit and outputting the digital signal. Each of the first to the (N?1)-th stages (101 to 10N?1) includes an analog-digital converter circuit including comparators comparing an analog signal with reference potential being determined in advance and mutually different in parallel. The first to the (N?1)-th stages are in redundant configuration with the comparators of the stage including an auxiliary comparator.

Abstract: A semiconductor device manufactured by forming a plurality of first trenches in each of which a trench gate is formed, in an epitaxial layer of a first conductivity type; implanting an impurity of a second conductivity type into a part beneath each of the first trenches to form a first column region; and implanting an impurity of the second conductivity type into a part beneath a base region formed between the first trenches to form a second column region. The first and second column regions are formed with an impurity concentration such that a total depletion charge in the regions is substantially equal to a depletion charge in the epitaxial layer.

Abstract: A self-refresh control circuit includes a first constant current generating circuit that generates a constant current to change depending on the temperature, a second constant current generating circuit to generate a constant current not depending on the temperature, a current-cycle converting circuit selectively connected to the first constant current generating circuit and the second constant current generating circuit and converting the constant currents inputted from the first constant current generating circuit and the second constant current generating circuit into a test refresh cycle used for setting the refresh cycle.

Abstract: A semiconductor device having good production stability and excellent in a contact property between an antireflection film on an Al contained metal film and a conductive plug. The device includes a substrate, an insulating interlayer, and a multi-layer structure. The insulating interlayer is formed in the upper portion of the substrate. The structure is provided on the insulating interlayer. A Ti film, a first TiN film, an AlCu film, a Ti film, a second TiN film, and an etching adjustment film are sequentially formed in the structure. The device includes an insulating interlayer and a conductive plug. The insulating interlayer is provided on the insulating interlayer and the structure. The conductive plug penetrates the insulating interlayer and the etching adjustment film, and an end surface of the conductive plug is located in the second TiN film. The conductive plug includes a Ti film, a TiN film, and a W film.

Abstract: A semiconductor device in which a DRAM and a SRAM are mixedly mounted is provided. The DRAM and the SRAM have a stack-type structure in which a bitline is formed below a capacitive element. A cross couple connection of the SRAM is formed in a layer or below the layer in which a capacitive lower electrode of the DRAM is formed and in a layer or above the layer in which the bitline is formed. For example, the cross couple connection of the SRAM is formed in a same layer as a capacitive contact.