Abstract: A semiconductor device includes a plurality of PMOS transistors formed on a semiconductor substrate; and a plurality of NMOS transistors formed on the semiconductor substrate. The plurality of PMOS transistors are electrically isolated from each other by a device isolation structure formed in the semiconductor substrate. The plurality of NMOS transistors are continuously formed in a first direction such that a sequence of N-type diffusion layers of the plurality of NMOS transistors extends in the first direction. One of the plurality of PMOS transistors and one of the plurality of NMOS transistors share a gate electrode.

Abstract: In a semiconductor circuit device including a first terminal adapted to receive a first voltage and a second terminal adapted to receive a second voltage lower than the first voltage, a capacitive circuit and a short-circuit preventing circuit are provided in series between the first and second terminals. In this case, when the capacitive element is in an insulating (non-conductive) state, the short-circuit preventing circuit is in a conductive state, while, when the capacitive circuit is in a conductive state, the short-circuit preventing circuit is in an insulating state.

Abstract: A semiconductor integrated circuit device has memory macros and logic cores. The memory macro is composed of a dynamic memory including an access port and a refresh port. The semiconductor integrated circuit device also has a refresh control circuit common for a plurality of the memory macros. The refresh control circuit has a refresh address generation circuit which generates a refresh address for a memory macro having the largest capacity, supplies the refresh address to the memory macro, and supplies given top bits of the refresh address as a refresh address to another memory macro having a smaller capacity.

Abstract: A semiconductor device has a multi-layer wiring in which resistance against migration of the semiconductor device is raised to improve the yield. Semiconductor device 100 includes a first interconnect (wiring) 112, formed in a first interlayer insulating film 106 on a semiconductor substrate, not shown, a via 128 provided on the first interconnect (wiring) 112 so that the via is connected to the first interconnect (wiring) 112, and a different element containing electrically conductive film 114. The different element containing electrically conductive film is formed selectively on a site on the top of the first interconnect (wiring) 112 where the first wiring is contacted with the bottom of the via 128. The different element containing electrically conductive film contains a metal of a main component of the first interconnect (wiring) 112 and a different element different from the metal of the main component.

Abstract: To conduct a reliability test for a tape automated bonding (TAB) package under a state being close to a mounting state to a product, the TAB package (1) includes a TAB tape (3), a semiconductor chip (2) mounted on the TAB tape (3), and a first terminal (7a) and a second terminal (7b) formed on both end portions of the TAB tape (3), electrically connected to the semiconductor chip (2) through wiring. A test board (10) used for the reliability test for the TAB package (1) includes a substrate (20), a pair of holding members (30-1, 30-2) provided on the substrate 20 so as to face with each other for holding the respective both end portions of the TAB package (1), holding portion terminals each provided to each of the pair of holding members (30-1, 30-2) so as to have a contact with each of the first terminal (7a) and the second terminal (7b).

Abstract: A frequency synthesizer includes first and second frequency dividers for receiving and frequency-dividing a signal generated by a voltage-controlled oscillator, a frequency mixer for mixing output signals of the first and second frequency dividers, and a third frequency divider for receiving and frequency-dividing a signal having one frequency of two frequencies that are output by the frequency mixer. The first, second third and frequency dividers and the frequency mixer are provided in a feedback loop within a PLL circuit between the voltage-controlled oscillator and the phase comparator. The phase comparator has a first input terminal to which a signal to which a signal that is output by the third frequency divider is input and a second input terminal to which a reference clock signal that is output by a reference signal generator is input. A loop filter supplies the voltage-controlled oscillator with a voltage that is based upon result of the phase comparison by a phase comparator.

Abstract: A semiconductor device (100) includes: a substrate (102); a bonding pad (110) provided above the substrate (102); and an inductor (112) provided above the substrate (102) and below the bonding pad (110) for carrying out signal transmission/reception to/from the external in a non-contact manner by electromagnetic induction.

Abstract: A Phase-Locked Loop (PLL) circuit includes a voltage-controlled oscillator. The voltage-controlled oscillator includes a voltage-current conversion circuit and a current-controlled oscillation circuit. The voltage-current conversion circuit includes an input transistor having a gate terminal connecting a control voltage, a first transistor connected in series to the input transistor, a second transistor connected as a current-mirror to the first transistor, to generate a control current, and a current source connected in parallel to the first transistor. The current-controlled oscillation circuit oscillates at a frequency according to the control current.

Abstract: A semiconductor device includes a first conductive type first transistor, a first conductive type second transistor, a first power supply pad arranged between the first transistor and the second transistor and supplying a first potential, a second conductive type third transistor, a second conductive type fourth transistor, a second power supply pad arranged between the third transistor and the fourth transistor and supplying a second potential, a first output pad arranged between the first transistor and the third transistor, and a second output pad arranged between the second transistor and the fourth transistor, in which a direction in which a line connecting the first power supply pad with the second power supply pad extends is perpendicular to a direction in which a line connecting the first output pad with the second output pad extends.

Abstract: An apparatus includes a first selector which selects a test data during a first operation mode, and selects a first input data during a second operation mode, a first latch circuit which latches an output signal of the first selector according to a first clock signal, a second selector which selects one from a second input data and an output signal of the first latch circuit, and a second latch circuit which latches the second input data sent from the second selector according to a second clock signal during the second operation mode, and passes through the output signal of the first latch circuit sent from the second selector during the first operation mode.

Abstract: A power supply circuit includes a control circuit which outputs a control signal when an in-rush current flows and a power-supply-resistance control circuit which supplies a current to a capacitive load. The power-supply-resistance control circuit, provided in the current path between a power supply and the capacitive load, increases the resistance of the current path in response to the control signal and reduces the resistance of the current path in response to a stop page of the control signal, whereby the control signal is output or stopped so that the in-rush current is suppressed to a value smaller than or equal to a given value.

Abstract: To provide a semiconductor storage device capable of reducing the number of ECC bits. A semiconductor storage device according to an embodiment of the invention includes a memory cell array, an ECC cell storing ECC bits, and an ECC computating circuit calculating the ECC bits, which calculates first ECC bits as the ECC bits for first data including at least one write data and a part of read data that is read from the memory cell array.

Abstract: A wiring board has a base insulating film. The base insulating film has a thickness of 20 to 100 ?m and is made of a heat-resistant resin which has a glass-transition temperature of 150° C. or higher and which contains reinforcing fibers made of glass or aramid. The base insulating film has the following physical properties (1) to (6) when an elastic modulus at a temperature of T° C. is given as DT (GPa) and a breaking strength at a temperature of T° C. is given as HT (MPa). (1) A coefficient of thermal expansion in the direction of thickness thereof is 90 ppm/K or less. (2) D23?5 (3) D150?2.5 (4) (D?65/D150)?3.0 (5) H23?140 (6) (H?65/H150)?2.3.

Abstract: A memory controller includes a variable delay circuit for phase-shifting a signal and an interface circuit suited for performing a test of a controller so that the memory controller realizes a test of a delay failure detection in a real-time speed operation at the time of the test.

Abstract: A method for manufacturing a semiconductor device or a semiconductor wafer using a chucking unit is provided to remove a slurry that adheres to the back surface of the semiconductor wafer. An edge portion of a semiconductor wafer is polished while a back surface of the semiconductor wafer is chucked to a chucking unit of a first polishing unit. The polished semiconductor wafer is then dechucked from the chucking unit of the first polishing unit. Next, a gap is formed above the chucking unit of the second polishing unit, and the semiconductor wafer is disposed therein. Water is discharged from the chucking unit of the second polishing unit to clean the back surface of the semiconductor wafer W. Thereafter, the back surface of the semiconductor wafer is chucked to the chucking unit of the second polishing unit, and the semiconductor wafer is polished.

Abstract: An interface circuit includes a variable delay circuit and a delay adjustment circuit to automatically detect a data valid window of a DQ signal and adjust an optimum delay amount of a DQS signal, and a fixed delay circuit to delay the DQ signal by a delay amount tFIXDLY satisfying tFIXDLY>tMINDLY+tSKEW?tSETUP where a minimum delay amount in the variable delay circuit is tMINDLY, a skew between the DQ signal and the DQS signal is tSKEW, and a setup time of the DQ signal is tSETUP.

Abstract: A clock distribution circuit for distributing an input clock according to an embodiment of the present invention includes: a first clock buffer receiving the clock; a first clock mask series-connected to the first clock buffer and controlling clock input to the first clock buffer; a second clock buffer series-connected to the first clock buffer and receiving a clock output from the first clock mask; and a second clock mask series-connected to the first clock buffer and the second clock buffer to control clock input to the second clock buffer.

Abstract: A semiconductor device includes a semiconductor substrate, a copper-containing metal interconnect over the semiconductor substrate, and a copper-containing connection plug, and the metal interconnect includes metal elements other than copper, and a concentration of different metal elements in a connection portion between the metal interconnect and the connection plug is higher than a concentration of the different metal elements in a center portion of the metal interconnect, and higher than a concentration of different elements in upper face portion of the metal interconnect other than the connection portion.

Abstract: The method of manufacturing a semiconductor device according to the present invention includes: forming an interconnect trench in an insulating film formed on a semiconductor substrate (S100); forming a barrier metal layer on the whole surface of the insulating film (S102); forming a copper layer on the whole surface of the barrier metal layer so that the copper layer is embedded in the interconnect trench (S104); removing the copper layer outside the interconnect trench by polishing under a condition that the barrier metal layer is left on the surface of the insulating film (S106); selectively forming a cap metal layer on the copper layer formed in the interconnect trench after the step of removing the copper layer by polishing (S108); and flattening the cap metal layer by polishing (S110).

Abstract: There has been a problem that the distortion characteristic of a switch circuit for a high frequency is deteriorated. A switch circuit in accordance with one aspect of the present invention includes a transistor connected in series between input and output terminals, a control terminal that receives a signal to control the conductive state of the transistor, a first resistor connected between the control electrode of the transistor and the control terminal, and a series circuit of a diode and a second resistor, the series circuit being connected in parallel with the first resistor between the control terminal and the control electrode of the transistor.