Abstract: In a semiconductor photo-detecting element (an avalanche photodiode), a high-sensitivity element is obtained by incorporating a multiplication layer having high-performance multiplication characteristics. By using a structure which reduces an electric field applied to an etching stopper layer, it is possible to use a multiplication layer having higher-performance multiplication characteristics (a multiplication layer which performs multiplication with a high electric field). The first method to realize this is to use a conductivity type multiplication layer. The second method is to use a structure in which a field buffer layer of the second conductivity type is incorporated. As a result of the use of these methods, a structure which applies an electric field lower than the multiplier electrical field to the etching stopper layer is obtained.

Abstract: A fault diagnosis method for a semiconductor device in which a memory and a register are monolithically integrated is provided. The fault diagnosis method is composed of: first testing the memory with respect to a series of addresses to identify a first error address; externally outputting the first error address; storing the first error address into the register; second testing the memory with respect to a series of addresses; identifying a second error address different from the first error address using a result of the second testing and the first error address stored in the register; externally outputting the second error address; and updating the register to store the second error address.

Abstract: A wireless receiving apparatus according to an embodiment of the invention can communicate with a wireless transmitting apparatus that implements a closed-loop transmit diversity scheme using a first antenna and a second antenna. An antenna verification unit of the wireless receiving apparatus verifies a weight vector added to at least one of a signal sent from the first antenna and a signal from the second antenna by the wireless transmitting apparatus based on feedback information from the wireless receiving apparatus.

Abstract: An oxide film formed on the surface of copper film of an electrode pad is cleaned by oxalic acid after unevenness is formed on the surface of copper film by treating the surface with organic acid. Thereby, stable resistance is obtained when carrying out a characteristic inspection by bringing a probe into contact with the electrode pad, and it is easily recognized by observation through a microscope that the probe is brought into contact with the electrode pad. In addition, wettability with respect to solder is satisfactory, and it is possible to favorably form a solder bump on the electrode pad.

Abstract: Disclosed is a processor apparatus including a branch condition storage unit having a plurality of storage regions in each of which a branch condition set by a condition setting instruction is stored, an instruction decoder that decodes an instruction code, an instruction memory that stores therein the instruction code, an operation register used by a processor for operation, a branch condition comparison unit that performs a comparison operation for each of branch conditions, a conditional branch determination unit that makes a determination whether or not to perform program branching in a conditional branch instruction, a selector that makes selection between a branch destination address and a next instruction address, based on an output value of the condition branch determination unit, and a program counter that indicates a processor instruction executing position.

Abstract: An improved migration resistance of the interconnect is provided and a diffusion of silicon into the inside of the interconnect is suppressed. A semiconductor device includes a silicon substrate, a first insulating film provided on the silicon substrate and composed of an SiCN film, an SiOC film and an SiO2 film, and a first copper interconnect provided in the first insulating film and essentially composed of a copper-containing metal. An Si—O unevenly distributed layer doped with injected silicon is included in the vicinity of the surface in the inside of the first copper interconnect, and injected atomic silicon at least partially creates Si—O bond.

Abstract: A semiconductor circuit is installed on a printed circuit board having a power wiring pattern and a ground wiring pattern that do not intersect. The semiconductor circuit includes a first power supply terminal and a first ground terminal for a first side of the semiconductor circuit, and a second power supply terminal and a second ground terminal for a second side opposing to the first side. The direction from the first power supply terminal to the first ground terminal is the same as the direction from the second power supply terminal to the second ground terminal.

Abstract: To provide wiring structure and method capable of supplying a scan clock signal for each clock domain without requesting a user to add a test circuit. The wiring structure of a semiconductor integrated circuit according to an embodiment of the present invention includes: a fixed layer where a common line independent of a user circuit is formed; and a customized layer which is formed on the fixed layer and in which a line dependent on the user circuit is formed. The fixed layer is provided with a scan clock line supplying a scan clock signal for scan test to the selecting circuit, and a clock line supplying an output signal of the selecting circuit to a flip-flop of a scan path, and the customized layer is provided with a user clock line supplying a user clock signal to the selecting circuit.

Abstract: In an embodiment of the invention, if a microprocessor detects runaway of a CPU executing a program, it starts a recovery program. The runaway in the program execution is detected by monitoring accesses a non-implementation space in a program space. If the CPU accesses any address in the non-implementation space, the microprocessor sends an instruction to the CPU to execute a predetermined recovery program. Thereby, the microprocessor can detect and stop the runaway into the non-implementation space.

Abstract: A semiconductor device has a semiconductor substrate having an impurity-diffused region and a device isolation insulating film formed in the surficial portion thereof, a gate electrode formed on the semiconductor substrate, a contact formed on the gate electrode and connected to the gate electrode, and a protective film disposed between the semiconductor substrate and the gate electrode, below the connecting portion between the gate electrode and the contact, formed wider in width than the gate electrode in a sectional view taken along the direction of gate length of the gate electrode.

Abstract: An operational amplifier according to an embodiment of the present invention includes: an operational amplifier stage executing differential-amplification of an input voltage and a reference voltage; a source-grounded amplifier stage outputting the differential-amplified signal; a phase compensation capacitance compensating for a phase of an output signal; and a charge/discharge control circuit controlling charge/discharge of the phase compensation capacitance.

Abstract: A semiconductor apparatus generates a clock signal used for scan test on an internal circuit of the semiconductor apparatus. The semiconductor apparatus includes a scan chain for performing input and output of data in the internal circuit, a clock generator for generating a launch clock signal for sending data to the internal circuit and a capture clock signal for capturing data from the internal circuit. The launch clock signal and the capture clock signal are generated based on a plurality of clock signals having different phases, and a pulse width of the plurality of clock signals is smaller than half of a cycle of the plurality of clock signals.

Abstract: A step-down circuit is connected between a power supply node for supplying a supply voltage and an internal power supply line for supplying a power to the object circuit and steps-down the supply voltage, and supplies the stepped-down voltage to the object circuit through the internal power supply line. The step-down circuit includes a comparison circuit that compares a reference voltage with the voltage of the internal power supply line, and a driver that adjusts a current flowing between the internal power supply line and the power supply node according to the comparison result of the comparison circuit. The activity level of the driver is controlled so as to rise in a predetermined rising period synchronously with an activated operation of the object circuit and to fall in a predetermined falling period that comes after the rising period.

Abstract: An output port circuit includes a plurality of output buffers; a plurality of first holding circuits configured to hold output data to be outputted to the plurality of output buffers; a plurality of second holding circuits configured to hold output data to be outputted to the plurality of first holding circuits; and a plurality of third holding circuits configured to hold bit pattern data for individually setting whether the output data of the plurality of second holding circuits are latched by the plurality of first holding circuits. Data input to the plurality of second holding circuits and data input to the plurality of third holding circuits are controlled at a same timing.

Abstract: A instruction execution part of an information processing device outputs an access request including a first address information to specify an access destination based on an execution of an access command of an address space in a memory. The instruction execution part also outputs a check request including a second address information to specify a stack pointer point after extension based on an execution of a stack extension command to extend a stack included in the address space in the memory by updating a stack pointer. A protection violation detection section of the information processing device detects whether the access destination includes the plurality of the partial spaces by collating the first information with the memory protection information stored in the memory protection information storage section.

Abstract: Leakage current flowing into load is prevented when a charge pump circuit operation is halted. The charge pump circuit converts supply voltage, supplied to a supply-voltage input terminal, to an output signal having desired voltage value and outputs the signal to an output terminal. A first bypass circuit, connected between the supply-voltage input terminal and a supply node of the charge pump circuit, forms a bypass between the supply-voltage input terminal and the supply node only when a voltage value at the supply node is low compared with a supply voltage value supplied to the supply-voltage input terminal. A second bypass circuit connected between the output terminal and the supply node, forms a bypass between the output terminal and the supply node only when the voltage value at the supply node is low compared with the voltage value at the output terminal.

Abstract: A read circuit includes: an integration circuit section configured to perform an integral operation and whose input is connected to an integration node; and a bias circuit connected between a connection node to which a variable resistive element is connected and the integration node. The bias circuit includes: an integration transistor whose source and drain are respectively connected to the connection node and the integration node; an operational amplifier whose output is connected to a gate of the integration transistor, to whose first input a bias voltage is supplied, and whose second input is connected to the source of the integration transistor; and a current switching circuit configured to provide or shut off a first current path. The first current path is a current path through which a current flowing between the drain and source of the integration transistor flows without passing through the connection node.

Abstract: In a circuit simulation system, a storage section is configured to store a circuit data, an analysis condition data and an output data. An initial data setting section reads out the circuit data and the analysis condition data from the storage section and sets an initial data and a convergence condition for a solution calculating process based on the circuit data and the analysis condition data. A processing section generates a circuit equation to each of a voltage variable and a current variable based on the circuit data, and executes the solution calculating process based on the initial data to calculate a solution. A convergence determining section executes a convergence determining process of whether or not the solution meets the convergence condition, on the voltage variable. An output section stores the solution into the output data when it is determined to meet the convergence condition.

Abstract: A nonvolatile semiconductor memory device includes a semiconductor substrate, a select gate formed above the semiconductor substrate, a floating gate formed above the semiconductor substrate and an erase gate positioned lower than an upper surface of the floating gate, and opposite an edge of a lower surface of the floating gate.

Abstract: A semiconductor integrated circuit device includes a first chip including an internal circuit, and a second chip capable of being accessed only via the first chip, and a test processor circuit electrically connected internally via the first chip, for accessing the second chip from an external terminal and testing the second chip, and a test circuit where an input/output buffer is installed for signals for accessing the second chip within the test processor circuit, and a bypass line installed for transferring signals from the first chip to the second chip and avoiding the input/output buffer within the test processor circuit, and a switch which switches between signal transfer path via the input/output buffer, and a signal transfer path via the bypass line.