Abstract: In a power supply control apparatus for controlling supplying of power from a battery to a load, a power supply switch circuit chip is connected to the load, to turn ON and OFF a connection between the battery and the load. A control circuit chip is powered by the battery to control the power supply switch circuit chip. The control circuit chip is constructed by an internal circuit for controlling the power supply switch circuit chip, a parasitic diode connected in parallel to the internal circuit, and a depletion type MOS transistor connected in series to the internal circuit. Diode characteristics of the parasitic diode and the depletion type MOS transistor are opposite to each other with respect to the battery. That is, in a forward-connected battery state, the parasitic diode and the depletion type MOS transistor are reverse-biased and forward-biased, respectively.

Abstract: A liquid crystal display includes: a plurality of scanning lines; a plurality of data lines overlapping the plurality of scanning lines at a plurality of intersection regions; a plurality of pixels located at the plurality of intersection regions; and a scanning line driver configured to drive the plurality of pixels by sequentially scanning the plurality of scanning lines. The plurality of scanning lines include a first scanning line and a second scanning line. The plurality of pixels include a first pixel associated with the first scanning line and a second pixel associated with the second scanning line. The scanning line driver drives the second pixel after the first pixel in a first period, and drives the first pixel after the second pixel in a second period.

Abstract: A bolt includes a main body and a spring pin. The main body includes a head and a shaft. The spring pin includes a base portion and an end portion. The shaft includes a portion of external thread and a hollow portion. The head includes a top surface and a hole opened in the top surface. The hole is connected to the hollow portion. The base portion is arranged in the hollow potion to move along an axis of the main body. The end portion is arranged in the hole to move along the axis. The spring pin is energized toward a side of the head such that the end portion protrudes beyond the top surface. The end portion is electrically connected to the portion of external thread.

Abstract: An N-type deep well is used to protect a circuit from a noise. However, a noise with a high frequency propagates through the N-type deep well, and as a result, the circuit that should be protected malfunctions. To reduce the area of the N-type deep well. For instance, in the present invention, a semiconductor device comprises a semiconductor substrate of a first conductivity type, a digital circuit part and an analog circuit part provided on the semiconductor substrate, a plurality of wells of the first conductivity type formed in either the analog circuit part or the digital circuit part, and a first deep well of a second conductivity type, which is the opposite conductivity type to the first conductivity type, isolating some of the plurality of wells from the semiconductor substrate.

Abstract: A heatsink plate is to be fixed to a substrate with sufficient strength, so as to prevent the heatsink plate from being stripped off, to thereby secure reliability on the performance of the semiconductor chip. The heatsink plate has both the upper and lower surfaces of the fixing section sandwiched by an adhesive resin. Such structure provides an increased adhesion area between the heatsink plate and the upper surface of the substrate, thereby securing greater fixing strength compared with the conventional structure in which simply the lower surface of the heatsink plate and the upper surface of the substrate are adhered to each other. Accordingly, the heatsink plate can be fixed to the upper surface of substrate with greater strength.

Abstract: A flip-chip type semiconductor device includes a semiconductor substrate. A plurality of electrode terminals are provided and arranged on a top surface of the semiconductor substrate, a sealing resin layer is formed on the top surface of the semiconductor substrate such that the electrode terminals are completely covered with the sealing resin layer.

Abstract: A semiconductor wafer 1 has first scribe lines 31 in two mutually perpendicular directions which have a first width and divide the semiconductor wafer 1 into a plurality of areas; second scribe lines 32 which have a second width smaller than the first width and divide the area into a plurality of semiconductor chip areas 2; an electrode pad 5 formed along the edge of the semiconductor chip area 2; and a metal-containing accessory pattern 4 disposed in the scribe lines. In the second scribe lines 32, the accessory pattern 4 is absent in at least the outermost surface in an area adjacent to the edge having the electrode pad 5 in the chip area 2.

Abstract: A charger of the present invention includes a charging transistor and a charging integrated circuit. The charging transistor is series-connected with a secondary battery to supply a charging current to the secondary battery. The charging integrated circuit is incorporated into a package having a higher heat releasability than that of the charging transistor. The charging integrated circuit controls the charging transistor and besides, supplies a charging current to the secondary battery. For this purpose, the charging integrated circuit includes a current source supplying this charging current. The charging current from the current source is supplied to the secondary battery together with the charging current from the charging transistor to charge the secondary battery.

Abstract: In a pulse width modulation circuit, a multiphase clock generation section generates a multiphase clock signal according to a reference clock. Then, a pulse width modulation signal is generated according to input data and the multiphase clock signal generated by the multiphase clock generation section. The multiphase clock generation section has a phase lock loop circuit and generates the multiphase clock signal by phase-interpolating an intermediate clock signal generated by the phase lock loop circuit.

Abstract: The communication device according to the present invention is a direct sequence spread spectrum device that performs a communication by using multiple different spread codes for multiple symbols. The direct sequence spread spectrum device according to the present invention includes: a correlation unit that calculates a correlation between each of the multiple different spread codes and a received signal spread by each of the multiple different spread codes, and that outputs a correlation degree for each of the spread codes; and a determination unit that demodulates the received signal to a symbol based on a value of the correlation degree for each of the spread codes.

Abstract: Disclosed herewith is a wiring substrate for releasing a heat generated by an electronic part efficiently through a heat pipe. The wiring substrate of the present invention includes a built-in heat pipe. The substrate also has amounting area. In the mounting area, an IC chip is mounted on a mounting surface. The substrate has a heat pipe formed so that its distance from the mounting area with respect to the mounting surface becomes shorter than its distance from an outside area provided outside the mounting area.

Abstract: A radio receiver includes a frequency converter, an oscillation circuit, an A/D converter, and a digital demodulator. The A/D converter digitally samples the intermediate frequency signal by using one of an oscillating frequency, a multiplying frequency, and a dividing frequency of the clock signal as a sampling frequency. The digital demodulator performs a digital demodulation processing by using the intermediate frequency signal digitally sampled and by using the one of the oscillating frequency, the multiplying frequency, and the dividing frequency of the clock signal as an operating frequency. The oscillating frequency is within a predetermined range. The predetermined range is at least one of equal to or more than 37.1 MHz and less than or equal to 37.9 MHz, equal to or more than 54.1 MHz and less than or equal to 64.8 MHz, and equal to or more than 74.2 MHz and less than or equal to 75.8 MHz.

Abstract: Disclosed is a level shift circuit including a first level shift circuit that is connected between a first power supply terminal and first and second output terminals and receives first and second input signals from the first and second input terminals, respectively, and sets one of the first and second output terminals to a first voltage level, based on the first and second input signals; a second level shift circuit that is connected between a second power supply terminal and the first and second output terminals, and sets the other of the first and second terminals to a second voltage level; and a circuit that performs control to disconnect a current path in the second level shifter between the second power supply terminal and one of the first and second output terminals that is driven to the second voltage level at a time point when the first and second input signals are supplied to the first and second input terminals for a predetermined period including the time point when the first and second input sig

Abstract: A layout design device includes a calculation processing portion that calculates a degree of wire congestion of each layer based on a pre-wiring design data to form a desired wiring structure in each layer, a selection processing portion that selects one area from a plurality of areas as a selection area, and an adding processing portion that generates a post-addition design data by adding a design data which connects the power supply and ground including layer and the (n?1)th layer or the (n+1)th layer to the pre-wiring design data. A degree of wire congestion of the selection area of nth layer is lower than that of (n?1)th layer or (n+1)th layer, the selection processing portion selects a power supply and ground including layer which is a lower layer of the (n?1)th layer or an upper layer of the (n+1)th layer and has a power supply or a ground. A wiring process and a metal generating process are performed based on the post-addition design data.

Abstract: A socket for a semiconductor device which can be used in a multipurpose manner with plural semiconductor device having electrode terminals of varying shapes. The socket for a semiconductor device according to an embodiment of this invention has a contact terminal placing an electrode terminal of the semiconductor device in abutment and electrical connection, an IC mount mounting a substrate face forming an electrode terminal of the semiconductor device, and an adjustable IC mount shifting unit enabling adjustment of a separation distance of an upper surface of the contact terminal and an upper surface of the IC mount in order to maintain normal electrical connection between the contact terminal and an electrode terminal of the semiconductor device irrespective of the shape of an electrode terminal of the semiconductor device.

Abstract: A semiconductor device has gate electrodes disposed in plural columns, respectively, over a semiconductor substrate in such a way as to be lined up along the direction of a gate length, and a gate connection portion provided in the same layer where the respective gate electrodes in the plural columns are placed, for electrically connecting the gate electrodes with each other. The gate connection portion includes a protrusion protruding outward in the direction of the gate length from the gate electrode positioned at the outermost ends of the gate electrodes disposed in the plural columns, respectively.

Abstract: A delay control circuit in which steady phase error can be eliminated has a first variable delay circuit and a first phase control circuit. The delay control circuit further includes a second variable delay circuit disposed in either a first or second clock path, and a second phase control circuit arranged so as to form an additional feedback loop, which is for canceling steady phase error produced by the first phase control circuit, with respect to the first clock path or second clock path using a delay value applied to the second variable delay circuit.

Abstract: A package for an electronic component including a chip mounting area mounting a semiconductor chip in a hollow part of a metal plate and a plurality of connection electrodes to be connected to a substrate. The plurality of connection electrodes are formed in opposite sides of the rectangular metal plate and arranged asymmetrically with respect to a perpendicular bisector of the opposite sides.

Abstract: A VLIW digital signal processor is composed of a program memory including first to n-th banks, first to n-th address counters, a fetch block, and an instruction executing section. The first to n-th banks store therein first to n-th programs, respectively. The first to n-th address counters respectively indicates addresses at which next instructions to be executed next, selected out of VLIW instructions within said first to n-th programs, are stored in said first to n-th banks. The fetch block is configured to fetch said next instructions from said addresses, respectively, and to generate a resultant VLIW instruction from said next instructions. The instruction executing section is configured to receive said resultant VLIW instruction, and to execute said resultant VLIW instruction in a single instruction executing cycle.

Abstract: A receiver is constructed by a signal reception circuit including a first amplifier section adapted to generate a first current in response to a first input signal and a second amplifier section adapted to generate a second current in response to a second input signal, to thereby generate an amplification signal in accordance with a difference between the first and second currents, and a feedback signal generating circuit adapted to generate a feedback signal in accordance with the amplification signal. Driving abilities of the first and second amplifier sections are determined in accordance with the feedback signal.