Abstract: A system, method, and computer program product are provided for generating primitive-specific attributes. In operation, it is determined whether a portion of a graphics processor is operating in a predetermined mode. If it is determined that the portion of the graphics processor is operating in the predetermined mode, only one or more primitive-specific attributes are generated in association with a primitive.

Abstract: A system and method are provided for dynamically reducing power consumption of floating-point logic. A disable control signal that is based on a characteristic of a floating-point format input operand is received and a portion of a logic circuit is disabled based on the disable control signal. The logic circuit processes the floating-point format input operand to generate an output.

Abstract: One embodiment of the present invention sets forth a technique for launching work on a processor. The method includes the steps of initializing a first state object within a memory region accessible to a program executing on the processor, populating the first state object with data associated with a first workload that is generated by the program, and triggering the processing of the first workload on the processor according to the data within the first state object.

Abstract: A method for identifying entry points of a hierarchical structure having a plurality of nodes includes the operations selecting a node of a hierarchical structure and testing it for identification as an entry point. The node is identified as an entry point, and the selection, testing, and identification operations are repeated for at least one additional node of the hierarchical structure to identify at least a second node as a respective second entry point for the hierarchical structure.

Abstract: Cache hit information is used to manage (e.g., cap) the prefetch distance for a cache. In an embodiment in which there is a first cache and a second cache, where the second cache (e.g., a level two cache) has greater latency than the first cache (e.g., a level one cache), a prefetcher prefetches cache lines to the second cache and is configured to receive feedback from that cache. The feedback indicates whether an access request issued in response to a cache miss in the first cache results in a cache hit in the second cache. The prefetch distance for the second cache is determined according to the feedback.

Abstract: The MMU services data requests associated with isochronous (ISO) data (referred to herein as “ISO requests”) with a high priority to meet a fixed latency requirement. Such data includes display data for transmission to the display device or other display devices. Conversely data requests associated with non-isochronous (NISO) data are serviced with a relatively lower priority. Such data requests include requests received from the CPU, video requests and copy requests. The MMU utilizes a buffering mechanism to buffer ISO and NISO requests. The size of the buffer that stores ISO requests controls the amount of memory bandwidth that is allocated to the ISO requests and the amount of memory bandwidth available for NISO requests.

Abstract: A graphics system includes an integrated graphics processor and a discrete graphics processing unit. An intra-system bus coupled data from the discrete graphics processing unit to the integrated graphics processor. In a high performance mode the discrete graphics processing unit is used to render frames. Compression techniques are used to aid in the data transfer over an intra-system bus interface.

Abstract: A method of generating white noise for use in graphic and image processing, in accordance with one embodiment of the present invention, includes receiving one or more hash inputs. The hash inputs may be one or more primitive coordinates, one or more texel addresses, a base image, a device identifier, or a user password. The one or more hash inputs are evaluated utilizing a cryptographic hash function. The output of the cryptographic hash function generates one or more white noise samples. The white noise samples may be utilized as texel data. The white noise samples may also be utilized for encrypting images.

Abstract: One embodiment sets forth a technique for dynamically mapping addresses to banks of a multi-bank memory based on a bank mode. Application programs may be configured to perform read and write a memory accessing different numbers of bits per bank, e.g., 32-bits per bank, 64-bits per bank, or 128-bits per bank. On each clock cycle an access request may be received from one of the application programs and per processing thread addresses of the access request are dynamically mapped based on the bank mode to produce a set of bank addresses. The bank addresses are then used to access the multi-bank memory. Allowing different bank mappings enables each application program to avoid bank conflicts when the memory is accesses compared with using a single bank mapping for all accesses.

Abstract: A system, method, and computer program product are provided for multi-sample processing. The multi-sample pixel data is received and an encoding state associated with the multi-sample pixel data is determined. Data for one sample of a multi-sample pixel and the encoding state are provided to a processing unit. The one sample of the multi-sample pixel is processed by the processing unit to generate processed data for the one sample that represents processed multi-sample pixel data for all samples of the multi-sample pixel or two or more samples of the multi-sample pixel.

Abstract: Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.

Abstract: An exemplary system of the present disclosure comprises a memory controller, a command bus, a data bus, a memory device and a memory. The memory device is coupled to the memory controller by the command bus and the data bus. The memory stores instructions that when executed by the computer system perform a method of requesting data from the memory device. This method comprises receiving a plurality of commands for the memory device from the command bus, the memory device clocked by a clock. At least one command of the plurality of commands includes a first command and a second command within a single clock cycle of said clock. At least one of the first command and second command is a data access command. The first command is executed during a first clock cycle and the second command is executed during a second subsequent clock cycle.

Abstract: While an application is still running and using a resource that the application has already allocated, real-time capture is used to allow for a minimal overhead, quick turnaround solution for debugging and performance analysis. Application programming interface interception can be used to construct a database of resource usage that can then be mined for dependencies.

Abstract: Embodiments of the present invention are directed to provide a method and system for applying automatic power conservation techniques in a computing system. Embodiments are described herein that automatically limits the frame rate of an application executing in a discrete graphics processing unit operating off battery or other such exhaustible power source. By automatically limiting the frame rate in certain detected circumstances, the rate of power consumption, and thus, the life of the current charge stored in a battery may be dramatically extended. Another embodiment is also provided which allows for the more effective application of automatic power conservation techniques during detected periods of inactivity by applying a low power state immediately after a last packet of a frame is rendered and displayed.

Abstract: A graphics card is provided. The graphics card comprises: a Graphics Processing Units (GPU) for data computing; and a wireless controller for wirelessly receiving data from other graphic cards or sending data to the other graphics cards, and communicating with the GPU by bus. The graphic card able provided by the present invention can provide a low-cost solution with more powerful computing capabilities to meet the demands for computing complex problems in the fields of commerce, industry, and science.

Abstract: A system, method, and computer program product for scheduling tasks associated with continuation thread blocks. The method includes the steps of generating a first task metadata data structure in a memory, generating a second task metadata data structure in the memory, executing a first task corresponding to the first task metadata data structure in a processor, generating state information representing a continuation task related to the first task and storing the state information in the second task metadata data structure, executing the continuation task in the processor after the one or more child tasks have finished execution, and indicating that the first task has logically finished execution once the continuation task has finished execution. The second task metadata data structure is related to the first task metadata data structure, and at least one instruction in the first task causes one or more child tasks to be executed by the processor.

Abstract: A system and method are provided for measuring an integrated circuit age. A first clock generator is provided for generating a first clock signal and a second clock generator is provided for generating a second clock signal. Further, a phase detector in communication with the first clock generator and the second clock generator is provided for receiving the first clock signal from the first clock generator and the second clock signal from the second clock generator, and outputting a phase difference signal that is capable of being used as a measure of an integrated circuit age. Still yet, a circuit in communication with the phase detector and the first clock generator is provided for receiving the first clock signal from the first clock generator and the phase difference signal from the phase detector and for synchronizing the phase difference signal from the phase detector with the first clock signal from the first clock generator.

Abstract: The present invention provides a rear cover of a flat panel electronic device and a flat panel electronic device having the rear cover. A outer surface of the rear cover is provided with a recess and a supporting leg, the supporting leg is pivotably connected in the recess through a pivot means so as to enable the supporting leg to pivot between a retracting position and an unfolding position, the supporting leg is configured to be contained in the recess when being in the retracting position, and to make an angle with the rear cover when being in the unfolding position, a speaker is disposed in the supporting leg, sound holes are disposed at a position on a side wall of the supporting leg which is corresponding to the speaker, a through-hole is formed at a position of the rear cover which is corresponding to the pivot means, and an electric wire of the speaker passes through the through-hole to extend into the rear cover.

Abstract: A method includes detecting, through a processor communicatively coupled to a memory, coupling of an external display to a data processing device including an internal display, and cloning, through the processor, display data of the internal display on the external display following the detection of the coupling. The method also includes triggering, through a driver component, the processor to turn off a backlight of the internal display of the data processing device, power gate circuitry associated with rendering the display data on the internal display and/or power gate a processing pipeline associated with the rendering of the display data following the cloning. Further, the method includes maintaining, through the driver component, a touchscreen capability of the internal display even when the backlight is turned off, the circuitry associated with the rendering of the display data is power gated and/or the processing pipeline associated therewith is power gated.

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a cache memory, and a package. The first processing unit comprises a first ground-referenced single-ended signaling (GRS) interface circuit and the second processing unit comprises a second GRS interface circuit. The cache memory comprises a third and a fourth GRS interface circuit. The package comprises one or more electrical traces that couple the first GRS interface to the third GRS interface and couple the second GRS interface to the fourth GRS interface, where the first GRS interface circuit, the second GRS interface, the third GRS interface, and the fourth GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.