Abstract: A three-dimensional stereo display, and a system and method are provided for controlling the three-dimensional stereo display. The three-dimensional stereo display includes backlight, a first polarizer, a first liquid crystal panel, a second polarizer and a second liquid crystal panel which are sequentially arranged on the backlight source. The second liquid crystal panel switches the polarizing angle of the light travelling through and exiting from said second liquid crystal panel between a horizontal and vertical polarization. Due to the polarization direction of light could be changed by the liquid crystal panel, and makes the light for the left-eye image and the right-eye image are mutual perpendicular. The polarization direction of the light for the left-eye image is the same as that of the left lens, and the polarization direction of the light for the right-eye image is the same as that of the right lens.

Abstract: A method includes providing, in a data processing device including a Central Processing Unit (CPU) and a Graphics Processing Unit (GPU), a capability to interface a microprocessor with the GPU, and communicatively interfacing a sensor with the microprocessor. The method also includes obtaining data related to an operating environment external to the data processing device through the sensor, and determining, through the microprocessor, personalization required of a computing environment of the data processing device with respect to a user thereof based on the data related to the operating environment external to the data processing device. Further, the method includes utilizing the GPU solely to effect the personalization required of the computing environment of the data processing device with respect to the user determined through the microprocessor to reduce power consumption through the data processing device.

Abstract: A system, method, and computer program product are provided for calculating settings for a device, utilizing one or more constraints. In use, a plurality of parameters associated with a device is identified. Additionally, one or more constraints are determined, utilizing the plurality of parameters. Further, one or more settings are calculated for the device, utilizing the one or more constraints and the plurality of parameters.

Abstract: A system, method, and computer program product are provided for allowing a head to enter a reduced power mode. A first processor having a first head is provided. Additionally, a second processor having a second head is provided. Furthermore, a link is provided, coupled between the first head of the first processor and the second head of the second processor for communicating first data therebetween. In operation, at least the second head of the second processor is capable of entering a reduced power mode.

Abstract: A system, method, and computer program product for recovering from a memory underflow condition associated with generating video signals are disclosed. The method includes the steps of determining that a first counter is greater than a second counter, incrementing an address corresponding to a memory fetch request by an offset, and issuing the memory fetch request to a memory. The first counter represents a number of pixels that have been read by a display pipeline for a current frame and the second counter represents a number of pixels requested from a memory for the current frame.

Abstract: One embodiment of the present invention sets for a method for accessing data objects stored in a memory that is accessible by a graphics processing unit (GPU). The method comprises the steps of creating a data object in the memory based on a command received from an application program, transmitting a first handle associated with the data object to the application program such that data associated with different graphics commands can be accessed by the GPU, wherein the first handle includes a memory address that provides access to only a particular portion of the data object, receiving a first graphics command as well as the first handle from the application program, wherein the first graphics command includes a draw command or a compute grid launch, and transmitting the first graphics command and the first handle to the GPU for processing.

Abstract: A system and device are provided for implementing memory arrays using high-density latch cells. The device includes an array of cells arranged into columns and rows. Each cell comprises a latch cell that includes a transmission gate, a pair of inverters, and an output buffer. Each row of latch cells is connected to at least one common node for addressing the row of latch cells, and each column of latch cells is connected to a particular bit of an input signal and a particular bit of an output signal. A register file may be implemented using one or more arrays of the high-density latch cells to replace any or all of the banks of SRAM cells typically used to implement the register file.

Abstract: A system, method, and computer program product for generating executable code for performing large integer operations on a parallel processing unit is disclosed. The method includes the steps of compiling a source code linked to a large integer library to generate an executable file and executing the executable file to perform a large integer operation using a parallel processing unit. The large integer library includes functions for processing large integers that are optimized for the parallel processing unit.

Abstract: A system and method are provided for protecting data. In operation, a request to read data from memory is received. Additionally, it is determined whether the data is stored in a predetermined portion of the memory. If it is determined that the data is stored in the predetermined portion of the memory, the data and a protect signal are returned for use in protecting the data. In certain embodiments of the invention, data stored in the predetermined portion of the memory may be further processed and written hack to the predetermined portion of the memory. In other embodiments of the invention, such processing may involve unprotected data stored outside the predetermined portion of the memory.

Abstract: A system and method are provided for generating an adaptive clock signal, configured to track prevailing operating conditions within an integrated circuit. The method comprises transmitting a first signal edge to a row of cells within a memory instance, waiting for two or more selected cells within the row of cells to propagate corresponding responses based on the first signal edge, and generating a memory delay signature signal edge based on the corresponding responses. The adaptive clock signal is generated based on the delay signature signal edge.

Abstract: A method and a system are provided for performing memory access assist using voltage boost. A memory access request is received at a storage cell array that comprises two or more subarrays, each subarray including at least one row of storage cells. The voltage boost is applied, during the memory access, to a first negative supply voltage of a first storage cell subarray of the two or more storage cell subarrays. The first negative supply voltage of the first storage cell subarray is lower than a second negative supply voltage of a second storage cell subarray of the two or more storage cell subarrays.

Abstract: A system, method, and computer program product for implementing an algorithm for performing thin voxelization is disclosed. The thin voxelization algorithm receives a surface, maps the surface onto a plurality of volumetric picture elements (voxels), and generates a value for each voxel in the plurality of voxels that intersects with the surface. A voxel intersects with the surface when the surface intersects a crosshair shape associated with the voxel.

Abstract: A method includes initiating, through an interface of a data processing device, reverse playback of a video file stored in a memory of the data processing device. The method also includes causing, through a set of instructions associated with a processor of the data processing device communicatively coupled to the memory and/or an operating system executing on the data processing device, the processor to read frames corresponding to the video file in a reverse chronological order within a desired timeframe following the initiation of the reverse playback. Further, the method includes decoding, through the processor, each frame corresponding to the reverse chronological order for rendering thereof on the data processing device.

Abstract: A debugger graphical user interface (GUI) system, method, and computer program product are provided. In use, a list of constructs is displayed a first portion of the GUI of the debugger. Further, waveforms corresponding to the constructs or source code corresponding to the constructs is displayed in a second portion of the GUI of the debugger.

Abstract: One embodiment of the present invention sets forth a method for storing processed data within buffer objects stored in buffer object memory from within shader engines executing on a GPU. The method comprises the steps of receiving a stream of one or more shading program commands via a graphics driver, executing, within a shader engine, at least one of the one or more shading program commands to generate processed data, determining from the stream of one or more shading program commands an address associated with a first data object stored within the buffer memory, and storing, from within the shader engine, the processed data in the first data object stored within the buffer memory.

Abstract: A device comprises a processor arranged to automatically execute boot code upon start-up or reset. The boot code comprises a code authentication procedure to verify whether additional code is authenticated for execution on the processor. A separate security unit comprises a private unlock key and cryptography logic configured to use the private unlock key to sign a portion of data, thereby generating a signed unlock file for supply to a storage location. The processor is arranged to access the unlock file from the storage location, making it available without requiring connection to the security unit. The boot code further comprises an unlocking authentication procedure configured to check for the unlock file in the storage location, and if available to verify whether the unlock file is authenticated for use on the processor based on its signature, so as to de-restrict the boot authentication procedure on condition of verifying the unlock file.

Abstract: A subsystem configured to write data to a static random access memory cell employs a single N-channel MOS device connected to ground in each leg of the bi-stable memory cell to overdrive the stored data. The subsystem implements the dual control required to effect matrix operation of the SRAM cell in the gate circuit of the single N-channel MOS device in the drive path. Specifically, the column select signal controls a semiconductor junction that interrupts the data connection to the gate. In this manner, the column select control is removed from the drive path, thus increasing drive strength. Further, a second semiconductor junction connects the gate of the single NMOS device in the drive path when the gate signal is interrupted.

Abstract: A system, method, and computer program product are provided for a display multiplier. First image data is received for a first display device and second image data is received for a second display device, where the second display device has fewer scan lines than the first display device. A scan line of the second image data is duplicated and a display multiplier output stream is generated that includes a first scan line of the first image data, the scan line of the second image data, a second scan line of the first image data, and the duplicated scan line of the second image data.

Abstract: A surface cache stores pixel data on behalf of a pixel processing pipeline that is configured to generate screen tiles. The surface cache assigns hint levels to cache lines storing pixel data according to whether that pixel data is likely to be needed again. When the pixel data is needed to process a subsequent tile, the corresponding cache line is assigned a higher hint value. When the pixel data is not needed again, the corresponding cache line is assigned a lower hint value. The surface cache is configured to preferentially evict cache lines having a lower hint value, thereby preserving cache lines that store pixel data needed for future processing. In addition, a fetch controller is configured to throttle the rate at which fetch requests are issued to the surface cache to prevent situations where pixel data needed for future operations becomes prematurely evicted.

Abstract: Techniques are disclosed for generating stereoscopic images. The techniques include receiving a first image frame associated with a first eye, and receiving a first depth frame associated with the first eye. The techniques further include reprojecting the first image frame based on the first depth frame to create a second image frame associated with a second eye. The techniques further include identifying a first pixel in the second image frame that remains unwritten as a result of reprojecting the first image frame, and determining a value for the first pixel based on a corresponding pixel in a prior image frame associated with the second eye. One advantage of the disclosed techniques is that DIBR reprojected image frames have a more realistic appearance where gaps are filled using pixels from a prior image for the same eye.