Patents Assigned to NVidia
  • Publication number: 20140184583
    Abstract: A method for refreshing a display. The method includes refreshing even and odd columns of a display panel at a first frame refresh rate where for each frame, even and odd columns are refreshed. Upon entering a display idle period, a low power display refresh is performed. The low power display refresh includes: refreshing the even columns of the display during even frames while circuitry driving odd columns are not used, and refreshing the odd columns of the display during odd frames while circuitry driving the even columns are not used. Refreshing the even columns and refreshing the odd columns are performed at a second frame refresh rate that is slower than the first frame refresh rate.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: David Wyatt
  • Publication number: 20140184611
    Abstract: Embodiments of the present invention may include a graphics processor operable to generate video frames, wherein the graphics processor is operable to begin generating a partial update region of a video frame upon receiving a framelock signal. Further, a screen refresh controller may be communicatively coupled with the graphics processor, wherein the screen refresh controller is operable to receive partial update regions of video frames from the graphics processor and send framelock signals to the graphics processor. Additionally, a display device may be communicatively coupled with the screen refresh controller, wherein the display device is operable to receive and display video frames from the screen refresh controller.
    Type: Application
    Filed: December 31, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: David Wyatt, David Stears
  • Publication number: 20140185852
    Abstract: A portable electronic device is provided having an audio subsystem with a plurality of audio devices, each of which is coupled to a logic subsystem via its own audio path. The portable electronic device may also include a display configured to present visual content, with the display being fixed in position relative to the plurality of audio devices. The portable electronic device further includes an orientation sensor electronically coupled to the logic subsystem, the logic subsystem being configured, using data received from the orientation sensor, (i) to determine whether the portable electronic device has been reoriented; and (ii) in response to such determination, vary operation of one or more of the audio paths.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA Corporation
    Inventor: Mark Pereira
  • Publication number: 20140189452
    Abstract: A method for performing scan based tests is presented. The method comprises routing scan data serially from a plurality of I/O ports to a plurality of partitions of an integrated circuit using a first clock signal operating at a first frequency, wherein each partition comprises a plurality of internal scan chains. The method also comprises deserializing the scan data to feed internal scan chains. Further, the method comprises generating a plurality of second clock signals operating at a second frequency using the first clock signal, wherein each partition receives a respective one of the plurality of second clock signals and wherein the plurality of second clock signals are staggered wherein each pulses at a different time. Finally, the method comprises shifting in the scan data into the internal scan chains at the rate of the second frequency.
    Type: Application
    Filed: December 28, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Milind Sonawane, Satya Puvvada, Amit Sanghani
  • Publication number: 20140189316
    Abstract: In one embodiment, in an execution pipeline having a plurality of execution subunits, a method of using a bypass network to directly forward data from a producing execution subunit to a consuming execution subunit is provided. The method includes producing output data with the producing execution subunit, consuming input data with the consuming execution subunit, for one or more intervening operations whose input is the output data from the producing execution subunit and whose output is the input data to the consuming execution subunit, evaluating those one or more intervening operations to determine whether their execution would compose an identify function, and if the one or more intervening operations would compose such an identity function, controlling the bypass network to forward the producing execution subunit's output data directly to the consuming execution subunit.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Gokul Govindu, Parag Gupta, Scott Pitkethly, Guillermo J. Rozas
  • Patent number: 8768160
    Abstract: A flicker band automated detection system and method are presented. In one embodiment an incidental motion mitigation exposure setting method includes receiving image input information; performing a motion mitigating flicker band automatic detection process; and implementing exposure settings based upon results of the motion mitigating flicker band automatic detection process. The auto flicker band detection process includes performing a motion mitigating process on an illumination intensity indication. Content impacts on an the motion mitigated illumination intensity indication are minimized. The motion mitigated illumination intensity indication is binarized. A correlation of the motion mitigated illumination intensity and a reference illumination intensity frequency is established.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 1, 2014
    Assignee: Nvidia Corporation
    Inventors: Shang Hung Lin, Hu He, Ignatius B. Tjandrasuwita
  • Patent number: 8766989
    Abstract: The present invention provides a method and system for coordinating graphics processing units in a single computing system. A method is disclosed which allows for the construction of a list of shared display modes that may be employed by both of the graphics processing units to render an output in a display device. By creating the list of shared commonly supportable display modes, the output displayed in the display device may advantageously provide a consistent graphical experience persisting through the use of alternate graphics processing units in the system. One method builds a list of shared display modes by compiling a list from a GPU specific base mode list and dynamic display modes acquired from an attached display device. Another method provides the ability to generate graphical output configurations according to a user-selected display mode that persists when alternate graphics processing units in the system are used to generate graphical output.
    Type: Grant
    Filed: July 29, 2009
    Date of Patent: July 1, 2014
    Assignee: Nvidia Corporation
    Inventors: David Wyatt, Linda Glanville
  • Patent number: 8769413
    Abstract: A system, method and article of manufacture provide a multifunction toolbar for a web browser. A toolbar is displayed over a web browser. The toolbar is linked to a portal of a user. The portal is for aggregating content selected by the user. A bucket is presented on the toolbar. The present invention recognizes when the user selects content on a website, which is displayed on the web browser, and drops the content in the bucket. The selected content is added to the portal.
    Type: Grant
    Filed: August 17, 2001
    Date of Patent: July 1, 2014
    Assignee: NVIDIA International, Inc.
    Inventors: Christine Odero, Umair A. Khan, Rizwan M. Tufail, Sergey Zabelin, Carina J. Han, Haixiao Yu
  • Patent number: 8769569
    Abstract: A system, method, and computer program product are provided for delivering video content over a wide area network (WAN). Included is at least one server for transcoding or transrating the video content for delivery over the WAN.
    Type: Grant
    Filed: June 21, 2012
    Date of Patent: July 1, 2014
    Assignee: NVIDIA Corporation
    Inventors: Gerrit A. Slavenburg, Thomas F. Fox
  • Patent number: 8768642
    Abstract: The present invention systems and methods facilitate configuration of functional components included in a remotely located integrated circuit die. In one exemplary implementation, a die functional component reconfiguration request process is engaged in wherein a system requests a reconfiguration code from a remote centralized resource. A reconfiguration code production process is executed in which a request for a reconfiguration code and a permission indicator are received, validity of permission indicator is analyzed, and a reconfiguration code is provided if the permission indicator is valid. A die functional component configuration process is performed on the die when an appropriate reconfiguration code is received by the die. The functional component configuration process includes directing alteration of a functional component configuration. Workflow is diverted from disabled functional components to enabled functional components.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 1, 2014
    Assignee: Nvidia Corporation
    Inventors: Michael B. Diamond, John S. Montrym, James M. Van Dyke, Michael B. Nagy, Sean J. Treichler
  • Patent number: 8766988
    Abstract: One embodiment of the present invention sets forth a technique for providing state information to one or more shader engines within a processing pipeline. State information received from an application accessing the processing pipeline is stored in constant buffer memory accessible to each of the shader engines. The shader engines can then retrieve the state information during execution.
    Type: Grant
    Filed: October 6, 2010
    Date of Patent: July 1, 2014
    Assignee: NVIDIA Corporation
    Inventors: Jerome F. Duluk, Jr., Jesse David Hall
  • Patent number: 8769463
    Abstract: Embodiments of the claimed subject matter are directed to methods and a system that use a standardized grid of clock buffers to automatically route clocks according to a uniform clock grid throughout an ASIC of a non-uniform arrangement of non-uniformly sized logic partitions. According to one embodiment, clock sources and sinks are mapped to grid point locations and a novel grid routing process is performed to link them together. A clock routing macro is assigned to a corresponding partition and associated with the corresponding partition or logic unit according to a partition hierarchy. The underlying routing structure and resources of a clock routing macro are automatically renamed to correspond to the local partition in a script or schedule of programmed instructions, or a routing map. The position of blockages within a partition may also be detected and alternate routes for traversing the blockage may be preemptively determined as well.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: July 1, 2014
    Assignee: Nvidia Corporation
    Inventors: Clay Berry, Timothy J. McDonald
  • Patent number: 8768494
    Abstract: Embodiments of the invention provide a policy-based audio system. The system includes a sound application protocol interface, a configuration module and a speaker driver. The sound application protocol interface receives a set of sound samples generated by an application or event. The configuration module retrieves a first group of one or more parameters, rules and priorities applicable to the application or event. The speaker driver produces an audio output by processing the set of sound samples as a function of the group of one or more configuration parameters, rules and priorities.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: July 1, 2014
    Assignee: NVIDIA Corporation
    Inventors: Micah S. Stroud, Stephen G. Holmes, Edward L. Riegelsberger
  • Publication number: 20140181451
    Abstract: A method of training a command signal for a memory module. The method includes programming a memory controller into a mode wherein a single bit of an address signal is active for a single clock cycle. The method then programs a programmable delay line of the address signal with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
    Type: Application
    Filed: December 27, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Publication number: 20140176549
    Abstract: A deferred shading GPU, geometry data structure and method. One embodiment of the geometry data structure is found in a graphics processing subsystem operable to render a scene having a pixel represented by samples. The graphics processing subsystem includes: (1) a memory configured to store a geometry data structure associated with the pixel containing surface fragment coverage masks associated with the samples, and (2) a GPU configured to employ the surface fragment coverage masks to carry out deferred shading on the pixel.
    Type: Application
    Filed: December 21, 2012
    Publication date: June 26, 2014
    Applicant: Nvidia
    Inventor: Yury Uralsky
  • Publication number: 20140176578
    Abstract: An input output connector for a graphics processing unit having a graphics pipeline including fixed function units and programmable function units is disclosed. Additionally, a graphics processing unit and a method of operating a graphics pipeline are disclosed. In one embodiment, the input output connector includes: (1) a request arbiter configured to connect to each of the programmable function units, receive fixed function requests therefrom and arbitrate the requests and (2) fixed unit converters, wherein each of the fixed unit converters is dedicated to a single one of the fixed function units and is configured to convert the requests directed to the single one to an input format for the single one.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventor: Albert Meixner
  • Publication number: 20140181462
    Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Guillermo J. Rozas, Bharath Krishnan, James Van Zoeren
  • Publication number: 20140181391
    Abstract: A method of training chip select for a memory module. The method includes programming a memory controller into a mode wherein a command signal is active for a programmable time period. The method then programs a programmable delay line of the chip select with a delay value and performs initialization of the memory module. The memory module is then placed in a write leveling mode wherein placing the memory module in the write leveling mode toggles a state of the chip select. A write leveling procedure is then performed and a response thereto is determined from the memory module. A determination is made whether the memory module is in a pass state or an error state based on the response.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Venkata Ramana Malladi, Tony Yuhsiang Cheng, Sharath Raghava, Ambuj Kumar, Arunjit Sahni, Paul Lam
  • Publication number: 20140177693
    Abstract: An apparatus including a receiver coupled to receive an input signal from a communication link and operable to employ decision feedback equalization to the input signal of the communication link and generate an edge sample signal. The apparatus also includes a timing recovery module coupled to the receiver and operable to receive the edge sample signal and use the edge sample signal to generate a data sampling phase signal, wherein the edge sample signal influences a settling point of the data sampling phase signal.
    Type: Application
    Filed: December 26, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Lizhi Zhong, Vishnu Balan, Arif Al Amin, Sanjeev Maheshwari
  • Publication number: 20140176750
    Abstract: An approach is provided for performing back-end operations for camera control. In one example, a method includes the following: receiving a user edit via a user interface device that displays an interpretation of a scene at which a camera lens of the camera is pointing, wherein the user edit is based on user input that is associated with a selection region on the user interface device; generating an edits mask based on one or more matching image patches, which are based on the user edit and a high dynamic range (HDR) image generated by the camera; performing one or more tone mapping operations based on the edits mask and the HDR image in order to generate a tone mapped HDR image; and performing one or more metering operations based on the edits mask and the tone mapped HDR image in order to generate metering parameters for frame capturing operations.
    Type: Application
    Filed: March 1, 2013
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Dawid STANISLAW PAJAK, Jongmin BAEK, Kari PULLI