Abstract: A mobile computing device comprising a rotatable I/O port module that includes a plurality of I/O ports providing connections with external electronic devices. The I/O port module is rotatable in relative to the main body of the mobile device between a working state in which the I/O ports are externally accessible to a user and a hidden state in which the I/O ports are externally hidden. The rotation may be controlled by a user through any feasible manner, such as exerting a tangential force, a physical switch or an on-screen soft button, in association with suitable hardware and software components. The rotatable I/O port module may be physically coupled with the main body of the mobile computing device through a rotational axial connector which may also provides electrical connections between the rotational I/O module and the main body.

Abstract: A method of training a memory interface between a memory controller and a memory module. The method includes programming a delay line of a data strobe with a delay value and programming a reference voltage with a voltage value. The method then writes a data bit pattern to the memory module wherein the data bit pattern is of a first plurality of unique data bit patterns. The data bit pattern is read back and a result is compared with the data bit pattern. A determination is made whether the memory module is in a pass state or an error state based on the comparing. The steps are repeated with another data bit pattern of the first plurality of data bit patterns. The method is repeated for each combination of the data strobe delay value and the reference voltage value.

Abstract: A method for detecting an instruction ordering violation in a CPU. The method includes receiving a reordered stream of instructions and detecting whether an ordering violation has occurred by using virtual addresses. The method further includes transferring results of the reordered stream of instructions from a load store buffer into a cache and detecting whether an ordering violation has occurred by using physical addresses. Subsequently, a recovery is initiated upon detection of an ordering violation.

Abstract: A microelectronic package includes an interposer with through-silicon vias that is formed from a semiconductor substrate and one or more semiconductor dies coupled to the interposer. A first signal redistribution layer formed on the first side of the interposer electrically couples the one or more semiconductor dies to the through-silicon vias. A second redistribution layer is formed on a second side of the interposer, and is electrically coupled to the through-silicon vias. In some embodiments, a mold compound is connected to an edge surface of the interposer and is configured to stiffen the microelectronic package.

Abstract: One aspect provides a method for image correction. The method, in one embodiment, includes obtaining two or more simultaneously captured images of an object, wherein the two or more simultaneously captured images are of different perspectives of the object taken from an electronic device. The method, in this embodiment, further includes inputting the two or more simultaneously captured images into an image processing algorithm and generating a disparity map, and applying an image interpolation algorithm to the disparity map to obtain an interpolated image from a virtual camera location.

Abstract: One embodiment of the present invention sets forth a technique for detecting a video transition. The technique involves calculating a first average pixel intensity for each pixel grouping included in a first plurality of pixel groupings, calculating a second average pixel intensity for each pixel grouping included in a second plurality of pixel groupings, and calculating a third average pixel intensity for each pixel grouping included in a third plurality of pixel groupings. The technique further involves comparing a first average pixel intensity to a corresponding second average pixel intensity to identify a first trend, comparing a second average pixel intensity to a corresponding third average pixel intensity to identify a second trend, and comparing the first trend to the second trend to determine whether a match exits. Finally, the technique involves determining that a video transition is occurring based on a number of matches.

Abstract: A technique for managing processor cores within a multi-core central processing unit (CPU) provides efficient power and resource utilization over a wide workload range. The CPU comprises at least one core designed for low power operation and at least one core designed for high performance operation. For low workloads, the low power core executes the workload. For certain higher workloads, the high performance core executes the workload. For certain other workloads, the low power core and the high performance core both share execution of the workload. This technique advantageously enables efficient processing over a wider range of workloads than conventional systems.

Abstract: An apparatus and system are provided for implementing a hand-held device as a wireless mouse for controlling a wirelessly-connected device. The hand-held device includes a position sensor and includes an integrated case connected to the hand-held device. The case includes at least one button for providing user input.

Abstract: A graphics processing unit includes a set of geometry processing units each configured to process graphics primitives in parallel with one another. A given geometry processing unit generates one or more graphics primitives or geometry objects and buffers the associated vertex data locally. The geometry processing unit also buffers different sets of indices to those vertices, where each such set represents a different graphics primitive or geometry object. The geometry processing units may then stream the buffered vertices and indices to global buffers in parallel with one another. A stream output synchronization unit coordinates the parallel streaming of vertices and indices by providing each geometry processing unit with a different base address within a global vertex buffer where vertices may be written. The stream output synchronization unit also provides each geometry processing unit with a different base address within a global index buffer where indices may be written.

Abstract: A shadow softening GPU and method. One embodiment of the GPU is configured to render a shadow cast by a surface occluding a light source and includes: (1) a fetching circuit operable to retrieve a depth value from a texture associated with the surface and a depth comparison result in a single fetch operation, and (2) a shadow softening circuit configured to respectively employ the depth comparison result and the depth value to identify the surface as a blocker and attenuate the light source for a pixel.

Abstract: A technique for efficiently rendering content reduces each complex blend mode to a series of basic blend operations. The series of basic blend operations are executed within a recirculating pipeline until a final blended value is computed. The recirculating pipeline is positioned within a color raster operations unit of a graphics processing unit for efficient access to image buffer data.

Abstract: Systems and methods for coherency maintenance are presented. The systems and methods include utilization of multiple information state tracking approaches or protocols at different memory or storage levels. In one embodiment, a first coherency maintenance approach (e.g., similar to a MESI protocol, etc.) can be implemented at one storage level while a second coherency maintenance approach (e.g., similar to a MOESI protocol, etc.) can be implemented at another storage level. Information at a particular storage level or tier can be tracked by a set of local state indications and a set of essence state indications. The essence state indication can be tracked “externally” from a storage layer or tier directory (e.g., in a directory of another cache level, in a hub between cache levels, etc.). One storage level can control operations based upon the local state indications and another storage level can control operations based in least in part upon an essence state indication.

Abstract: In an integrated circuit device, a power circuit for maintaining asserted values on an input output pin of the device when a functional block of the device is placed in a sleep mode. The device includes a power circuit disposed along the periphery of the device, the power circuit configured to maintain power when the device is placed in a low-power mode. A plurality of input output blocks are included in the device and are for receiving external inputs for the integrated circuit device and for providing outputs from the integrated circuit device. The power circuit is coupled to provide power to at least one of the input output blocks to maintain state when the integrated circuit device is in the low-power mode.

Abstract: A system, process, and computer program product are provided for scanning a document with a hand-held device. An approach for scanning the document includes the steps of sampling one or more values from an array of sensors integrated into a hand-held device, determining whether the device has moved at least a threshold distance, and sampling one or more additional values from the array of sensors.

Abstract: One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication.

Abstract: A method of operating a graphics pipeline, a graphics processing unit and a GPU computing system are provided by this disclosure. In one embodiment, the graphics processing unit includes: (1) a processor configured to assist in operating the graphics processing unit and (2) a graphics pipeline coupled to the processor and including a programmable shader stage, the programmable shader stage configured to determine occurrence of a pipeline exception during execution of the graphics pipeline, initiate preempting the execution in response to determining the occurrence and initiate resolving the pipeline exception before execution is restarted.

Abstract: Techniques are disclosed for dispatching pixel information in a graphics processing pipeline. A fragment processing unit generates a pixel that includes multiple samples based on a first portion of a graphics primitive received by a first thread. The fragment processing unit calculates a first value for the first pixel, where the first value is calculated only once for the pixel. The fragment processing unit calculates a first set of values for the samples, where each value in the first set of values corresponds to a different sample and is calculated only once for the corresponding sample. The fragment processing unit combines the first value with each value in the first set of values to create a second set of values. The fragment processing unit creates one or more dispatch messages to store the second set of values in a set of output registers. One advantage of the disclosed techniques is that pixel shader programs perform per-sample operations with increased efficiency.

Abstract: A method for using an average motion vector in a motion vector search process. The method includes accessing an input frame for processing and reading average motion vector information from memory. The method further includes performing a motion vector search by using the average motion vector and a plurality of hints, calculating a winner motion vector based on the average motion vector and the plurality of hints, and storing the winner motion vector back into memory to create a new updated average motion vector. The method further includes finishing processing the input frame using the winning motion vector.

Abstract: Techniques are disclosed for dispatching pixel information in a graphics processing pipeline. A fragment processing unit in the graphics processing pipeline generates a pixel that includes multiple samples based on a portion of a graphics primitive received by a thread. The fragment processing unit calculates a set of source values, where each source value corresponds to a different sample of the pixel. The fragment processing unit retrieves a set of destination values from a render target, where each destination value corresponds to a different source value. The fragment processing unit blends each source value with a corresponding destination value to create a set of final values, and creates one or more dispatch messages to store the set of final values in a set of output registers. One advantage of the disclosed techniques is that pixel shader programs perform per-sample operations with increased efficiency.

Abstract: A facial image enhancement system includes a deformable face tracker that provides a tracked face model from a facial video stream. Additionally, the facial image enhancement system includes a face enhancement image processing engine that uses the tracked face model to process the facial video stream, wherein an image enhancement of the facial video stream provides an enhanced facial video stream. A facial image enhancement method is also provided.