Abstract: An apparatus and method for determining location information using a multi-polarized antenna array is disclosed. The multi-polarized antenna array includes a plurality of metal patches and a multiplexer. Each metal patch has at least two feed-points. The multiplexer is coupled to an RF terminal and to each of the at least two feed-points of each of the plurality of metal patches. The antenna array is configurable to couple each feed-point one at a time to the RF terminal. Location information may be determined by a controller coupled to the RF terminal from RF signals received via each feed-point.

Abstract: An electronic circuit includes a differential output circuit that produces a differential output signal at a differential output. A primary winding of a balun has a first balun terminal coupled to a first differential output terminal, and a second balun terminal coupled to a second differential output terminal. A configurable harmonic reduction circuit includes first and second configurable shunt capacitance circuits coupled between the first differential output terminal or the second differential output terminal, respectively, and a ground reference node. A control circuit receives tuning data associated with a calibrated tuning state. The tuning data indicates a first and second calibrated capacitance values, which are unequal, for the first and second configurable shunt capacitance circuits, respectively.

Abstract: A system-on-chip (SoC) includes a memory, a trust provisioning system, a one-time programmable (OTP) element, and a comparator. The memory is configured to store a first secret key before an execution of a trust provisioning operation. The trust provisioning system is configured to receive an encrypted version of a first set of secure assets and one of a second secret key and an encrypted version of the second secret key, and execute the trust provisioning operation on the SoC to store the first set of secure assets and the second secret key in the OTP element. The comparator is configured to compare the first and second secret keys to generate a valid signal that is indicative of a validation of the trust provisioning operation. The first set of secure assets and a second set of secure assets associated with the SoC are accessible based on the valid signal.

Abstract: A microelectromechanical systems (MEMS) accelerometer comprises a compliant spring structure with a first beam, a second beam, and a rigid structure. One end of the first beam and one end of the second beam are coupled to the rigid structure and a proof mass is coupled to another end of the second beam. Further, a spring anchor is coupled to another end of the first beam. In response to the proof mass moving, an extension coupled to the rigid structure moves in an opposite direction to motion of the proof mass to contact the proof mass and stop the movement of the proof mass.

Abstract: A method for dynamic enhancement of loop response upon recovery from fault conditions includes detecting a fault condition in response to a programmed output voltage of a Pulse Width Modulation (PWM) converter decreasing below an input voltage of the PWM converter. A peak voltage is sampled at the end of at least one of a plurality of clock cycles of the PWM converter in response to detecting the fault condition, wherein the peak voltage is proportional to a sensed current conducted through a transistor. An error output of an error amplifier is preset to an error value determined by the peak voltage. A PWM driver is controlled with the error value to drive the transistor. An output load is charged to the programmed output voltage with the transistor in response to the input voltage increasing above the programmed output voltage.

Abstract: A system to facilitate communication of a critical signal between functional circuitries of a system-on-chip utilizes a dynamic pattern to securely communicate the critical signal. The system includes selection and comparison circuits. The selection circuit is configured to select and output a set of dynamic pattern bits or a set of fixed reference bits, based on a logic state of the critical signal that is received from one functional circuitry. The comparison circuit is configured to output an output signal based on the set of dynamic pattern bits, and a set of intermediate bits that is derived from the set of dynamic pattern bits or the set of fixed reference bits. The output signal is provided to the other functional circuitry when a logic state of the output signal matches the logic state of the critical signal, thereby securely communicating the critical signal to the other functional circuitry.

Abstract: A data processing system includes a memory configured to receive memory access requests. Each memory access request having a corresponding access address and having a corresponding parity bit for an address value of the corresponding access address. The corresponding access address is received over a plurality of address lines and the parity bit is received over a parity line. The memory includes a memory array having a plurality of memory cells arranged in rows, each row having a corresponding word line of a plurality of word lines, and a row decoder coupled to the plurality of address lines, the parity line, and the plurality of word lines. The row decoder is configured to selectively activate a selected word line of the plurality of word lines based on the corresponding access address and the corresponding parity bit of a received memory access request.

Abstract: A no-gel sensor package is disclosed. In one embodiment, the package includes a microelectromechanical system (MEMS) die having a first substrate, which in turn includes a first surface on which is formed a MEMS device. The package also includes a polymer ring with an inner wall extending between first and second oppositely facing surfaces. The first surface of the polymer ring is bonded to the first surface of the first substrate to define a first cavity in which the MEMS device is contained. A molded compound body having a second cavity that is concentric with the first cavity, enables fluid communication between the MEMS device and an environment external to the package.

Abstract: A configurable control loop arrangement for forming a control loop of a DC-DC converter that is configured to generate a control signal to control the DC-DC converter, the configurable control loop arrangement comprising: a digital-to-analog converter; a comparator; a timer configured to provide a timing-signal for controlling one or more of: the comparator in the determination of the comparison signal; the application of the comparison signal to a configurable-event-generation-logic-module; and the operation of the configurable-event-generation-logic-module; wherein the configurable-event-generation-logic-module comprises a flip-flop circuit, and wherein the configurable-event-generation-logic-module, when implemented in the control loop, is configured to provide for generation of the control signal based on the comparison signal, the timing-signal and a selected mode of the flip-flop circuit, and wherein the control signal is for application to one or more switches of the DC-DC converter.

Abstract: A radar system, apparatus, architecture, and method are provided for generating a transmit reference or chirp signal that is applied to a waveform generator having a frequency offset generator and a plurality of single channel modulation mixers configured to generate a plurality of transmit signals having different frequency offsets from the transmit reference signal for encoding and transmission as N radio frequency encoded transmit signals which are reflected from a target and received at a receive antenna as a target return signal that is down-converted to an intermediate frequency signal and converted by a high-speed analog-to-digital converter to a digital signal that is processed by a radar control processing unit which performs fast time processing steps to generate a range spectrum comprising N segments which correspond, respectively, to the N radio frequency encoded transmit signals transmitted over the N transmit antennas.

Abstract: Embodiments of a method and an apparatus for wireless communications are disclosed. In an embodiment, a method for wireless communications involves, at a first station (STA), transmitting a first Physical Layer Protocol Data Unit (PPDU) that includes a first frame to a second STA, wherein the first frame indicates a first duration of a second PPDU that is transmitted subsequent to the first PPDU by a single STA, wherein a non-Trigger-Based (non-TB) PPDU format is used for the second PPDU, and wherein the first frame solicits a response frame included as part of the second PPDU, and at the first STA, receiving from the second STA, the second PPDU that includes the response frame.

Abstract: Embodiments of a calibration system for third order intermodulation distortion (IMD3) cancellation and a wireless apparatus are disclosed. In an embodiment, a calibration system for IMD3 cancellation includes a cancellation circuit for IMD3 cancellation between a first transmitter and a second transmitter, and a controller coupled to the cancellation circuit and configured to for each frequency channel of the first transmitter, perform a pre-conditional calibration of the cancellation circuit, after the pre-conditional calibration, determine a phase configuration for the cancellation circuit, and after the phase configuration for the cancellation circuit is determined, determine an attenuation configuration for the cancellation circuit.

Abstract: A semiconductor device and fabrication method are described for forming a nanosheet transistor device by forming a nanosheet transistor stack (12-18, 25) of alternating Si and SiGe layers which are selectively processed to form metal-containing current terminal or source/drain regions (27, 28) and to form control terminal electrodes (36A-D) which replace the SiGe layers in the nanosheet transistor stack and are positioned between the Si layers which form transistor channel regions in the nanosheet transistor stack to connect the metal source/drain regions, thereby forming a nanosheet transistor device.

Abstract: A method for self-calibration of reference voltage drop in a Digital to Analog Converter (DAC) includes measuring each one of a plurality of thermometric weightages associated with a respective one of a plurality of thermometric bits, wherein the DAC includes a plurality of sub-binary bits and the plurality of thermometric bits. For each sequentially increasing combination of thermometric bit settings including at least two thermometric bits coupled to a high reference voltage and each sub-binary bit coupled to a low reference voltage, performing the steps of: determining a respective combined weightage correction; adding the combined weightage correction to the highest order bit of the combination of thermometric bit settings; and incrementing a number of bits of the combination of thermometric bit settings in response to the number of bits of the sequential combination being less than a total number of the plurality of thermometric bits.

Abstract: A vehicle radar system, apparatus and method use a radar control processing unit generate compressed radar data signals, to apply the compressed radar data signals to a log detector to generate log detector sample values, and to generate a first log cell-average constant false alarm rate (CA-CFAR) threshold from the log detector sample values by computing and adding an average sample value SAVG from the log detector sample values, a probability of false alarm factor ?, and a log CA-CFAR correction factor ?, where the first log CA-CFAR threshold may be used with a second log CA-CFAR threshold to generate an ordered statistics CA-CFAR threshold for the compressed radar data signals by sorting the first and second log CA-CFAR thresholds by magnitude to form a sorted list of log CA-CFAR thresholds, and then selecting a kth threshold from the sorted list of log CA-CFAR thresholds as the OS-CA-CFAR threshold.

Abstract: A processing system including processors, peripheral slots, hardware resources, and gateway circuitry. Each processor is assigned a corresponding identifier. The peripheral slots are located within an addressable peripheral space. Each hardware resource is placed into a corresponding peripheral slot, including at least one direct memory access (DMA) device supporting at least one DMA channel and at least one general-purpose input/output (GPIO) pin. Memory protection and gateway circuitry is programmed to control access of the hardware resources only by a processor that provides a matching identifier. The memories along with hardware resources are protected against unauthorized accesses to isolate applications executed on each processor within a multicore system and hence support freedom of interference.

Abstract: A magnetoresistive random-access memory (MRAM) device includes an array of MRAM bit cells grouped into words, each word having specified number of data bit cells, error correction code (ECC) bit cells, and at least two inversion indicator bit cells, the inversion indicator bit cells being redundant of each other; and a memory controller. The memory controller is configured to, for each of the words, set the inversion indicator bit cells to indicate whether the number of data bit cells in a word having a zero value is greater than the number of data bit cells having a one value, invert the zeroes and ones in the bit cells when the inversion indicator bit cells are set to indicate a greater number of zeroes than ones in the data bit cells of the word, and revert the data bit cells to their value before the zeroes and ones were inverted.

Abstract: A processing system includes an interconnect, a master processing device including processing cores coupled to the interconnect, a hypervisor coupled to the interconnect and configured to allocate the processing cores to one or more virtual machines, domain configuration information including a domain identifier for each of the one or more virtual machines, remote peripheral devices coupled to the interconnect, and a domain access controller coupled to the interconnect and configured to receive the domain identifiers for the remote peripherals directly from the hypervisor through the interconnect.

Abstract: Embodiments of a method and an apparatus for a quadrature hybrid are disclosed. In an embodiment, a quadrature hybrid includes a first port, a second port, a third port, a fourth port, first, second, and third inductors, first, second, third, and fourth capacitors, and a first variable capacitor tuning network connected between the first port and the fourth port, and a second variable capacitor tuning network connected between the second port and the third port.

Abstract: Various embodiments relate to a method of multi-link operation between two multi-link devices (MLDs) where at least one MLD is a non-simultaneous transmit receive (NSTR) MLD that supports enhanced multi-link radio operation, including: operating, by the NSTR MLD, in a first operating mode, wherein the first operating mode is one of multi-link radio mode or enhanced multi-link radio mode; switching, by the NSTR MLD, between the first operating mode and a second operating mode, wherein the second operating mode is the multi-link radio mode when the first operating mode is the enhanced multi-link radio mode and the second operating mode is the enhanced multi-link radio mode when the first operating mode is the multi-link radio mode; announcing the operation capability by the NSTR MLD; and announcing the operating parameters by the NSTR MLD.