Abstract: A wireless communication device selectively flushes frames from a processing pipeline on a per-user basis. The wireless communication device stores frames (e.g., physical layer service data units (PSDUs)) of data for processing at one or more queues, wherein each frame is stored with the tag of the user associated with the frame. In response to an exception, such as a detected error or a user-reset request, the wireless communication device changes the tag of the user associated with the exception. When a frame is selected from a queue for processing at a pipeline, the wireless communication device compares the stored tag associated with the frame with the current tag associated with the user corresponding to the frame. In response to a mismatch, the wireless communication device discards the frame.

Abstract: In a System on a Chip (SOC) having multiple masters and multiple slaves connected to a bus via a crossbar switch, a time-based secure access control system of the SOC includes a central access control (CAC) circuit coupled to the master devices through respective channels to receive time-based access requests from the masters. Each slave is connected to a slave access control (SAC) circuit and each SAC circuit includes an access time control (ATC) circuit in communication with the CAC circuit and a dedicated timer. The CAC circuit controls the ATC circuits to limit the access permission from the masters to the slaves by checking whether a requested access time has expired.

Abstract: The embodiments described herein provide systems and methods for digital correction in low intermediate frequency (IF) receivers. Specifically, the embodiments described herein use digital correction techniques that can correct for signal distortions in low IF receivers caused by I-Q imbalance, including both I-Q magnitude imbalance and I-Q phase imbalance. In general, the embodiments described herein are implemented to at least partially cancel an image of a blocking signal in the complex digital signal. Such a cancellation can be implemented to at least partially cancel an image of blocking signal where that image occurs at or near the intermediate frequency. In one embodiment, a corrector is implemented in a low RF receiver and is configured to receive a complex digital signal that includes an image of a blocking signal. Such a low RF receiver can further include a trainer configured to train the corrector to generate the cancellation signal.

Abstract: A data processor comprises a memory-management-unit for receiving external-operation-data from a CPU. The memory-management-unit sets a deterministic-quantity value for the external-operation-data based on the external-operation-data. The deterministic-quantity value may be either an active-value or an inactive-value. The data processor has a non-deterministic-processor-block for receiving a memory-signal from the memory-management-unit, and has a control-block configured to (i) send the memory-signal to an NDP-output-terminal if the deterministic-quantity value is the active-value, thereby bypassing a performance-enhancement-block, or (ii) send at least a portion of the memory-signal that is representative of the request for response-data to the performance-enhancement-block if the deterministic-quantity value is the inactive-value.

Abstract: A calibration circuit for body biasing includes a phase detector, first and second voltage generators, and first and second voltage regulators. The phase detector has an input terminal configured to receive an oscillation signal from a ring oscillator. The phase detector provides output signals indicative of phase differences between the oscillation signal and a reference signal. The first voltage generator provides a first reference voltage using the output signals from the phase detector, and the first voltage regulator provides a first biasing voltage using the first reference voltage. The second voltage generator provides a second reference voltage using the first reference voltage, and the second voltage regulator provides a second biasing voltage using the second reference voltage. The first biasing voltage is used to bias P-wells of transistors in the ring oscillator, and the second biasing voltage is used to bias N-wells of transistors in the ring oscillator.

Abstract: An embodiment of a module (e.g., an amplifier module) includes a substrate, a transmission line, and a ground plane height variation structure. The substrate is formed from a plurality of dielectric material layers, and has a mounting surface and a second surface opposite the mounting surface. A plurality of non-overlapping zones is defined at the mounting surface. The transmission line is coupled to the substrate and is located within a first zone of the plurality of non-overlapping zones. The ground plane height variation structure extends from the second surface into the substrate within the first zone. The ground plane height variation structure underlies the transmission line, a portion of the substrate is present between the upper boundary and the transmission line, and the ground plane height variation structure includes a conductive path between an upper boundary of the ground plane height variation structure and the second surface.

Abstract: The present disclosure describes methods of encrypting and decrypting blocks of data stored in computer readable memory for a device using a block cipher with a nonce. In particular, methods of encrypting and decrypting blocks of data where the value of the nonce is based on previous execution instructions of a program executed by the device for a previously executed block are described. Embodiments disclosed include a method of encrypting blocks of data bits stored in computer readable memory for a device using a block cipher with a nonce and a key, the method comprising for each block of data: generating a value of the nonce based on previous execution instructions of a program executed by the device for a previously executed block of data; and encrypting the block of data with the nonce and key using the block cipher.

Abstract: An RF switch for connecting an antenna to a transceiver is described. The RF switch includes a first switchable capacitor arranged between a first terminal and a common terminal and a second switchable capacitor arranged between a second terminal and the common terminal. Each of the first and second switchable capacitors are switchable between a pass state and a blocking state. The capacitance value in the pass state is higher than the capacitance value in the blocking state.

Abstract: A first communication device allocates respective frequency sub-channels for subsequent orthogonal frequency division multiple access (OFDMA) communications with two or more second communication devices, including allocating a first frequency sub-channel, a second frequency sub-channel, and a third frequency sub-channel between the first frequency sub-channel and the second frequency sub-channel. The first communication device generates and transmits a first downlink OFDMA data unit configured to prompt the two or more second communication devices to transmit as part of a multi-user transmission that spans the first frequency sub-channel, the second frequency sub-channel, and the third frequency sub-channel. The first communication device receives an uplink OFDMA transmission and determines that the uplink OFDMA transmission did not include a transmission within the third frequency sub-channel.

Abstract: In a wireless charging system, a power-transmitting node (TX), has a processor, a memory, a power transmitter for transmitting power wirelessly to a power-receiving node (RX), and a signal receiver for receiving signals from the RX. After the processor detects the presence of a foreign object (FO) during a power-transfer session, the processor places the TX in a protection state. The processor detects whether the FO has been removed using quality factor (QF) values for the TX that the processor measures before and after detecting the presence of the FO, and without requiring any QF values calibrated off-line. The QF values include a QF value measured before the FO is present, a QF value measured just after the TX enters the protection state, and a current QF value that is repeatedly updated as long as the TX remains in the protection state.

Abstract: A method includes depositing a hardmask layer over a magnetoresistive (MR) structural layer formed on a substrate, the hardmask layer being formed from tungsten or a tungsten-based composition. A photoresist layer is deposited over the hardmask layer and is patterned to expose a first portion of the hardmask layer. A first etch process is performed to remove the first portion of the hardmask layer and expose a second portion of the MR structural layer and a dry etch process is performed to remove the second portion of the MR structural layer and produce an MR sensor structure. Following the dry etch process, a composite structure remains that includes the MR sensor structure and a hardmask section of the hardmask layer, the hardmask section overlying the MR sensor structure. A spacer formed from a protective, dielectric material layer may additionally be formed surrounding the composite structure.

Abstract: Internally-shielded microelectronic packages having increased resistances to electromagnetic cross-coupling are disclosed, as are methods for fabricating such microelectronic packages. In embodiments, the internally-shielded microelectronic package includes a substrate having a frontside and a longitudinal axis. A first microelectronic device is mounted to the frontside of the substrate, while a second microelectronic device is further mounted to the frontside of the substrate and spaced from the first microelectronic device along the longitudinal axis. An internal shield structure includes or consists of a shield wall, which is positioned between the first and second microelectronic devices as taken along the longitudinal axis. The internal shield structure is at least partially composed of a magnetically-permeable material, which decreases electromagnetic cross-coupling between the first and second microelectronic devices during operation of the internally-shielded microelectronic package.

Abstract: An electronic device, typically a microcontroller, which is divided into a multiplicity of power domains comprising one or more intelligent peripherals, is provided with an on-board power management module for switching power to one or more domains for pre-determined time periods and in a predetermined sequence. The values of the predetermined time periods and sequence may be pre-programmed by the design engineer or user of the device. In one example, power is switched to domains in a round robin fashion. An optional interrupt capability permits selective application of power to a dormant intelligent peripheral requesting it at the expense of others and based on a priority scheme. Consumption of current supplied to power domains may be monitored by a power watchdog or alternatively via a dedicated power monitor associated with each intelligent peripheral. The invention helps to reduce device power consumption without any associated reduction in processing performance.

Abstract: Exemplary aspects are directed to FM-radio circuitries and systems in which, at the receiving end of a broadcast transmission, circuitry is used set the bandwidth and band position for receiving the desired channel of the broadcast signal based on measured signal properties of immediately-adjacent channel(s). The adjustments to the received channel include bandwidth selection and offset frequency adjustment. These adjustments are, in part, based on USN signal levels as well as modulation symmetry detection which are affected by the modulation level of the desired and other channel(s). Signal processing circuitry such as logic/CPU circuitry, then receives the desired channel, including information carried by the broadcast signal, in response to setting the bandwidth based on the measured signal properties.

Abstract: Various embodiments relate to a PLL based FSK demodulator, the FSK demodulator comprising a PFD configured to receive an input signal, a fully differential auxiliary charge pump configured to receive and amplify the input signal from the PFD, a capacitor configured to filter the input signal from the auxiliary charge pump and a fully differential slicer configured to demodulate the input signal and output recovered data.

Abstract: An arbitrary rate digital decimator filter (204) and associated method are disclosed for filtering a digital data stream with a plurality of cascaded power-of-two decimator stages (205, 207) connected to receive the digital data stream and to generate a first filtered digital signal which is provided to a fractional resampling stage (211) which generates a second filtered digital signal with delta-sigma modulator (310) and a limited integrator stage (320) connected to receive a first control (301) word and a feedback clock signal (305) with inserted or swallowed pulses which is generated by a clock generator in response to pulse commands generated by the limited integrator stage, wherein the limited integrator is configured to generate time shift commands (303) to a timing shift filter (340) which performs fractional interpolation on the first filtered digital signal to generate the second filtered digital signal.

Abstract: Microelectronic systems and components having integrated heat dissipation posts are disclosed, as are methods for fabricating such microelectronic systems and components. In various embodiments, the microelectronic system includes a substrate having a frontside, a socket cavity, and inner cavity sidewalls defining the socket cavity. A microelectronic component is seated on the frontside of the substrate such that a heat dissipation post, which projects from the microelectronic component, is received in the socket cavity and separated from the inner cavity sidewalls by a peripheral clearance. The microelectronic system further includes a bond layer contacting the inner cavity sidewalls, contacting an outer peripheral portion of the heat dissipation post, and at least partially filling the peripheral clearance.

Abstract: One example discloses a near-field converter, including: a near-field magnetic antenna responsive to near-field magnetic signals; a near-field electric antenna responsive to near-field electric signals; wherein the converter is configured to, convert received near-field magnetic signals into and transmit as near-field electric signals; or convert received near-field electric signals into and transmit as near-field magnetic signals.

Abstract: A magnetoresistive random access memory (MRAM) array including MRAM cells arranged in rows and columns, wherein each MRAM cell has a select transistor and a Magnetic Tunnel Junction (MTJ). A plurality of rows of the MRAM array is configured as a single one-time-programmable (OTP) row having OTP cells, wherein the corresponding word lines of each row of the plurality of rows are electrically connected. In each column of the single OTP row, source electrodes of the select transistors in the corresponding MRAM cells in the column of the single OTP row are coupled to the corresponding source line, drain electrodes of the select transistors in the corresponding MRAM cells in the column of the single OTP row are electrically connected, and only a first MTJ of a first MRAM cell in the corresponding MRAM cells in the column of the single OTP row is connected to the corresponding bit line.

Abstract: A system and method for real-time data transfer on a system-on-chip (SoC) allows MIPI-CSI (camera serial interface) data received on a first interface to be output on another MIPI-CSI interface without using system memory or delaying the loopback path. The system includes a CSI receiver, a loopback buffer, and a CSI transmitter. The loopback buffer is used for the data transfer between the CSI receiver and the CSI transmitter. The CSI transmitter receives a payload included in a data packet from the CSI receiver by way of the loopback buffer. The CSI receiver communicates a packet header of the data packet to the CSI transmitter. The CSI transmitter reads the payload from the loopback buffer based on the packet header and at least one of a buffer threshold capacity and payload size.