Abstract: A lead frame used to assemble a semiconductor device, such as a smart card, has a first major surface including exposed leads and a second major surface including a die receiving area and one or more connection pads surrounding the die receiving area. The connection pads enable electrical connection of an Integrated Circuit (IC) die to the exposed leads. A molding tape sized and shaped like the lead frame is adhered to and covers the second major surface of the lead frame. The molding tape has a die receiving area cut-out that exposes the die receiving area and the connection pads on the second major surface of the lead frame and forms a cavity for receiving an encapsulant. The cut-out has an elevated sidewall for retaining the encapsulant within the cavity.

Abstract: A wireless multiple antenna system (200) uses a multi-antenna subsystem (211) to generate a composite sample waveform by continuously sweeping a plurality of receive beams (RX1-RXM) during each SSB transmission in a plurality of transmit beams (TX1-TX64), generating a composite received signal strength metric value from a batch of samples collected over the plurality of receive beams to determine the presence of the SSB, and then jointly searching the composite sample waveform for an optimal receive beam and an SSB frequency of any detected SSB that are used by the UE (210) to perform a cell search which matches a transmit beam from the base station (201) to the optimal receive beam.

Abstract: A radio frequency (RF) amplifier configured to operate at a fundamental frequency (f0) includes a transistor with a transistor output, an output matching network coupled to the transistor output, and a reflection absorption circuit. The output matching network includes an output path device connected between the transistor output and an output of the RF amplifier. The reflection absorption circuit is coupled between the transistor output and the output path device, and is configured to absorb reflected signal energy from the output path device.

Abstract: The embodiments described herein include amplifiers that are typically used in radio frequency (RF) applications. Specifically, the amplifiers described herein include one or more transient termination circuits coupled to transistor inputs. For example, the transient termination circuits can be configured to reduce the transient response for some signal energy at frequencies below a baseband frequency (fB) of signals being amplified while not similarly reducing the transient response for signal energy near a fundamental frequency (f0) of the signals being amplified.

Abstract: A signal converter includes a first converter, a second converter, a signal generator, and a controller. The first converter generates a first analog signal from a digital signal, and the second converter generates a second analog signal from the digital signal. The signal generator outputs a converted analog signal based on the first analog signal and the second analog signal. The controller generates one or more control signals to change a power supply state of at least one of the first converter and the second converter. The change in power supply state suppress even order harmonics.

Abstract: An example apparatus that employs circuitry operating in response to digital clock signal circuitry. The apparatus includes first circuitry and second circuitry. The first circuitry produces a high-frequency digital clock signal characterized by a high frequency which carries radiative noise interference and by a modulated low-frequency digital clock signal characterized by a low frequency modulated by a first type of modulation. The second circuitry produces another low-frequency digital clock signal by combining a disparate modulation signal and a feedback signal derived from the other low-frequency digital clock signal, wherein the disparate modulation signal is characterized by modulating the feedback signal via a second type of modulation that is independent of the first type of modulation and by cancellation/blocking of the radiative noise interference manifested by the circuitry operating in response to the digital clock signal circuitry.

Abstract: A data processing system configured to execute a plurality of threads includes a plurality of domains and a plurality of domain interrupt controller circuits, each domain interrupt controller corresponding to a domain of the plurality of domains. Each domain interrupt controller includes an interrupt selection circuit configured to select an interrupt request from a set of interrupt requests received by the interrupt selection circuit and determine an interrupt vector for the selected interrupt request, a programmable domain-thread storage circuit configured to store an enable indicator corresponding to each thread of the plurality of threads in which the enable indicator for each corresponding thread indicates whether or not the corresponding domain is permitted to route interrupt vectors to the corresponding thread, and a routing circuit configured to route the interrupt vector to a selected thread of the plurality of threads which is selected based at least in part on the enable indicators.

Abstract: A transceiver configured to send and receive data over a data bus is disclosed. The transceiver includes a communication port to connect to the data bus, a bus idle detector configured to detect when the data bus is idle, a TXDC interface configured to selectively receive and send data and an RXDC interface configured to send data. The transceiver also includes a switch controlled by an output of the bus idle detector. The switch is configured to cause the TXDC interface to be used for sending data out when the bus idle detector detects that the data bus is idle.

Abstract: A digital-to-analog converter (DAC) is described having a digital input, an analogue output, and two capacitors. The DAC has a controller. The controller is configured to generate a switching sequence including at least two switch cycles dependent on the input value received on the digital input. If the input value corresponds to an odd number, in a first switch cycle during a switch cycle first phase, the controller switchably couples a reference voltage to a first terminal and a ground voltage to a second terminal of one of the two capacitors, and switchably couples a ground voltage to a first terminal and the reference voltage to a second terminal of the other of the two capacitors. During a switch cycle second phase, the controller switchably couples a ground voltage to the first terminal and the analogue output to the second terminal of both capacitors.

Abstract: A protection module for an electronic circuit prevents unintended write operations by a master module to functional registers of a protected module. The protection module includes soft lock bits (SLBs) that indicate whether corresponding functional registers are locked and control logic that supports (i) a page select (PS) control parameter that indicates whether access by the master module is to the functional registers or the SLBs and (ii) a mode select (MS) control parameter that indicates whether access by the master module to the functional registers is in a normal access mode, in which each written-to functional register is left unlocked, or an auto-lock access mode, in which each just-written-to functional register is automatically locked by setting the corresponding SLB. The functional registers and the SLBs share addresses that can fit within a single address space that includes the control parameters.

Abstract: A chopper stabilized amplifier includes a first transconductance amplifier, first chopping circuitry coupled to an input of the first transconductance amplifier for chopping an input signal and applying the chopped input signal to the input of the first transconductance amplifier, and second chopping circuitry coupled to an output of the first transconductance amplifier for chopping an output signal produced by the first transconductance amplifier. A ping-pong notch filter is connected to an output of the second chopping circuitry and performs an integrate and transfer function on a chopped output signal produced by the second chopping circuitry to filter ripple voltages. The ping-pong notch filter includes parallel connected first and second notch filters, each of which has an input coupled to the output of the second chopping circuitry.

Abstract: A processing system, such as for an automobile, includes multiple processor cores, including an application core and a safety core, and a fault detection circuit in communication with the processor cores. The fault detection circuit includes a progress register for storing progress data of an application executed on the application core. The safety core, which executes a fault detection program, reads the progress data from the progress register, and generates an output based on the progress data and an expected behavior of the application. The safety core writes the output to a status register of the fault detection circuit. The fault detection circuit includes a controller that reads the status register and generates a fault signal when the output indicates there is a fault in the execution of the application. In response, the application core either recovers from the fault or runs in a safe mode.

Abstract: A plated hole with a sidewall plating. The plated hole has a vent opening that has a sidewall of non-conductive material that is not plated. During attachment of a joint conductive material such as solder to the sidewall plating, gasses generated from the attachment process are outgassed through the vent opening.

Abstract: A method of forming a transistor device where an extended drain region is formed by performing angled ion implantation of conductivity dopants of a first conductivity type into the sidewalls and bottom portion of a trench. The bottom portion of the trench is then implanted with dopants of a second conductivity type. Source and drain regions are formed on opposing sides of the trench including in upper portions of the trench sidewalls. A channel region is formed in a trench sidewall below the source region. The trench includes a control terminal structure. After formation of the transistor device, the net conductivity type of the bottom portion of the trench is of the first conductivity type.

Abstract: A first communication device configured is for communication with one or more second communication devices over a communication channel. The first communication device generates a first bandwidth indication of a first bandwidth of a first channel segment of the communication channel, and generates a second bandwidth indication, separate from the first bandwidth indication, of a second bandwidth of a second channel segment of the communication channel. The first channel segment does not overlap in frequency with the second channel segment. The first communication device generates one or more media access control protocol (MAC) data units to include the first bandwidth indication and the second bandwidth indication, and transmits the one or more MAC data units to the one or more second communication devices to indicate the first bandwidth of the first channel segment and the second bandwidth of the second channel segment to the one or more second communication devices.

Abstract: A radar unit (400) for detecting an existence of interference is described that includes: a millimetre wave (mmW) transceiver (Tx/Rx) circuit configured support a normal data acquisition mode of operation that comprises transmitting a radar signal waveform and receiving an echo signal thereof; a mixed analog and baseband circuit operably coupled to the mmW Tx/Rx circuit; and a signal processor circuit (452) operably coupled to the mixed analog and baseband circuit. An interference detection unit (448) is operably coupled to the mmW Tx/Rx circuit. The radar unit is configured to operate a time-discontinuous mode of operation that includes a first time portion used as an interference monitoring period and a second time portion used by the radar unit in the normal data acquisition mode of operation, whereby the mixed analog and baseband circuit, signal processor circuit (452) and interference detection unit (448) are configured to detect interference signals during the monitoring period.

Abstract: In a wireless charging system, a power-transmitting node (TX) has a power transmitter for transmitting power wirelessly to a power-receiving node (RX), a sampling and sensing circuit, a processor, and a signal receiver for receiving signals from the RX. The processor detects the presence of a foreign object (FO) during a power-transfer session using Quality Factor (QF) values. Estimated QF parameters are determined via exponential curve fitting using peak values of a damped sinusoidal waveform generated by a resonant circuit. Then the estimated parameters in the exponential curve are used to calculate the QF, which provides a robust measurement result even in a noisy environment.

Abstract: A hardware access control list (ACL) table is used to evaluate a received network packet to identify a first rule key portion in the hardware ACL table having a first address range indicator value that matches with an address value in the network packet, and the first rule key portion is then used to search a software-maintained list of extended check nodes linked with the first rule key portion to identify a first extended check node having a first address range value that matches with the address value in the network packet and to select one or more actions contained in the first extended check node to be performed by the networking element.

Abstract: A circuit for measuring temperature of an external switch is disclosed. The circuit includes a variable resistor, a switch coupled to the variable resistor in series, a fixed value resistor coupled to the variable resistor and a comparator coupled between the variable resistor and the fixed value resistor. The circuit is configured to compare voltage drop between a drain and a source of the external switch when the external switch is in ON state with voltage drop at the variable resistor and output a signal to indicate an overtemperature based on the comparing.

Abstract: A power control system, method, and architecture are disclosed for a multi-bank memory which provides independent, concurrent memory access to at least one memory block in each memory bank by using observation circuits to monitor bus masters connected over bus master interface signals to an interconnect for memory access requests to the multi-bank memory and to provide notifications to a power control circuitry that a valid memory access request was issued by a bus master over the bus master interface, where the power control circuitry processes the notifications received from each observation circuit and generates therefrom power control signals that are provided directly to each memory block and to bypass the interconnect, thereby separately controlling a power state for each memory block with power-up control signals that arrive at each memory block at or before a memory access request sent over the interconnect.