Abstract: A fully digital method and apparatus are provided for detecting glitches on a monitored line by providing a toggle signal to an initial delay circuit and a plurality of delay elements formed with standard logic cells so that logic values from the delay elements are captured in a corresponding plurality of clocked capture flops to provide a digitized representation of a delay value during a sampling period which is converted to a numerical measurement result which is evaluated against a reference value to generate an output error signal if a difference between the numerical measurement result and reference value exceeds a programmable margin, where the initial delay circuit is configured with a trim setting to impose an initial delay to compensate for process variations and where the reference value is adapted over a plurality of sampling periods to compensate for temperature effects on the numerical measurement result.

Abstract: A semiconductor device package is provided that incorporates an antenna structure within the package through use of three-dimensional additive manufacturing processes. Embodiments can provide semiconductor device packages that are thinner than traditional device packages by depositing specific metal and dielectric layers within the package in desired positions with precision that cannot be provided by other manufacturing techniques. Further, embodiments can provide antenna geometries and orientations that cannot be provided by other manufacturing techniques.

Abstract: A white-box system for authenticating a user-supplied password, including: a password database including a salt value and an authentication value for each user; a white-box implementation of a symmetric cipher configured to produce an encrypted value by encrypting the user-supplied password using the salt value associated with the user as an encoded secret key; and a comparator configured to compare the encrypted value with the authentication value associated with the user to verify the user-supplied password.

Abstract: A first communication device receives one or more aggregate medium access control (MAC) data units from respective one or more second communication devices, and generates one or more acknowledgement information fields. A first acknowledgement information field corresponds to a particular second communication device and includes a length indication that indicates a length of an acknowledgement field and the acknowledgment field of the indicated length. The length of the acknowledgement field is selected from a subset of predetermined lengths, among a set of predetermined lengths, the subset including multiple predetermined lengths that do not exceed a buffer size determined based on an acknowledgement setup procedure previously conducted between the first communication device and the particular second communication device.

Abstract: A method and apparatus of determining the position of a mobile device in a region of a vehicle cabin are described. The mobile device has a speaker and at least one microphone. The vehicle has an audio system comprising at least two speakers. The mobile device detects first and second acoustic signals respectively transmitted via the first and second vehicle speaker. The acoustic signals comprise a respective detection pattern. The detection patterns are mutually orthogonal. The detected acoustic signals may be compared or correlated with the detection patterns and a respective matched acoustic signal generated. The location of the mobile device within a region of the vehicle cabin may be determined based on the time difference of arrival of the first matched acoustic signal and the second matched acoustic signal. The mode of operation of the mobile device may be set or changed dependent on the location of the mobile device.

Abstract: A light emitting diode (LED) lighting system for an automobile includes a switch block, a capacitor, a charge pump, and a capacitor detector. The charge pump includes an output to provide power to a gate driver of the switch block at a nominal voltage level. The capacitor detector circuit includes a detector input and a detector output. The detector input is connected to the charge pump output and to the charge pump capacitor to detect a voltage level on the charge pump capacitor. The capacitor detector circuit provides a first indication on the detector output that the charge pump capacitor is present and undamaged when the voltage level is greater than the nominal voltage level. The capacitor detector circuit further provides a second indication on the detector output that the charge pump capacitor is not present or is damaged when the voltage level is less than the nominal voltage level.

Abstract: In a method of generating a field of a physical layer (PHY) preamble of a data unit, information bits to be included in the field are generated. Respective sets of tail bits are appended after respective sets of information bits corresponding to respective ones of a plurality of groups of subfields of the field, each group including one or more of the subfields of the field, to generate an encoder input bit stream. One or more padding bits are added to the encoder input stream to generate a padded encoder input bit stream, the one or more padding bits to ensure an integer number of puncturing blocks in an encoded output bit stream. The padded encoder input bit stream is encoded to generate the encoded output bit stream. The field is generated to include at least some bits from the encoded output bit stream.

Abstract: An arrangement for modifying a printed circuit antenna of the type used in mobile communication devices includes introducing one or more discontinuities into a printed circuit pattern of the antenna so that it is not activated at undesired frequencies. Examples of discontinuities include localized narrowing the printed circuit strip, localized widening of the printed circuit strip and localized changing of the shape of the printed circuit strip.

Abstract: An integrated circuit comprising: a plurality of on-chip-instrument-modules; a test-controller-module configured to communicate data with the plurality of on-chip-instrument-modules; a functional-module configured to communicate data with the plurality of on-chip-instrument-modules; and an on-chip-instrument-controller. The on-chip-instrument controller is configured to: for each of the plurality of on-chip-instrument-modules, store an access-indicator; and based on a value of the access-indicator for each on-chip-instrument-module, enable the on-chip-instrument-module to communicate with either: the test-controller-module; or the functional-module.

Abstract: A device includes a first signal line, a second signal line, and a controller. The first signal line is coupled to a first storage area. The second signal line is coupled to a second storage area. The controller outputs a signal to the first signal line or the second signal line to select the first storage area or the second storage area. The first storage area may be a removable data storage card, and the second storage area may be an embedded storage area in the device. The signal is a reset signal for the selected one of the first storage area and the second storage area.

Abstract: A mechanism is provided for detecting errors and parametric deviations in phase-locked loops (PLLs) by measuring the effectiveness of a PLL in recovering from an introduced delay in phase at a phase comparator of the PLL. Embodiments measure a proxy for the area under a phase difference recovery curve of the PLL. If the phase difference recovery is out of predefined thresholds for the PLL, then an error in the PLL is flagged or responded to. In some embodiments, the PLL is automatically re-trimmed to bring the PLL back within the predefined thresholds.

Abstract: A test system is provided. The test system includes a printed circuit board (PCB) and a plurality of integrated circuits (ICs) mounted on the PCB. A first IC of the plurality includes a first test circuit having a first test access port (TAP) controller. A second IC of the plurality includes a second test circuit having a second TAP controller and an embedded tester having a test data output coupled to a test data input of the first TAP controller by way of a link circuit. The embedded tester is configured to provide test control signals to the first TAP controller and the second TAP controller.

Abstract: A Doherty power amplifier includes input circuitry that provides input signals to carrier and peaking amplifiers with an input phase offset between 20 degrees and 160 degrees. Carrier and peaking amplifier output signals are combined at a combining node. A complex combining load matching circuit, which is connected to the combining node, consists of two, series-connected transmission line segments. The matching circuit provides a complex impedance, ZL, with a non-zero reactive portion, xn. The output circuit between the peaking amplifier and the combining node has an electrical length of 0 or n*180 degrees (n=an integer value). The output circuit between the carrier amplifier and the combining node has an electrical length, ?x, equal to an absolute value of the input phase offset when the electrical length of the peaking output circuit is 0 degrees.

Abstract: A successive approximation register, SAR, analog-to-digital converter, ADC, (400) is described. The SAR ADC (400) includes: a track and hold circuit (414) configured to sample an analog input signal (410); a comparator (416) coupled to the track and hold circuit and configured to compare the sampled analog input signal (410) with a DAC (444) output voltage; and a feedback path (422) that comprises a digital-to-analog converter, DAC, (444) configured to generate the reference voltage that approximates the input analog signal (410). The SAR ADC (400) further includes a dither circuit (468) coupled to or located in the feedback path (422) and arranged to add a dither signal at an input of the DAC (444) in a first time period and subtract the dither signal from the output digital signal routed via the feedback path (422) and input of the DAC (444) in a second time period during a conversion phase of the SAR ADC (400).

Abstract: Synchronizer circuits having controllable metastability are provided, one of which includes: a first flip-flop circuit comprising a first master latch connected in series with a first slave latch; and a second flip-flop circuit comprising a second master latch connected in series with a second slave latch, wherein an output of the first flip-flop circuit is connected to an input of the second flip-flop circuit, at least a portion of the first flip-flop circuit is implemented in a first PWell isolated by an underlying a deep isolation NWell, at least a portion of the first flip-flop circuit is implemented in a first NWell that electrically contacts the deep isolation NWell, the first NWell is connected to a first bias voltage that is less than a positive power supply voltage, and the first PWell is connected to a second bias voltage that is greater than a negative power supply voltage.

Abstract: An example analog-test-bus (ATB) apparatus includes a plurality of comparator circuits, each having an output port, and a pair of input ports of opposing polarity including an inverting port and a non-inverting port, a plurality of circuit nodes to be selectively connected to the input ports of a first polarity, and at least one digital-to-analog converter (DAC) to drive the input ports of the plurality of comparator circuits. The apparatus further includes data storage and logic circuitry that accounts for inaccuracies attributable to the plurality of comparator circuits by providing, for each comparator circuit, a set of calibration data indicative of the inaccuracies for adjusting comparison operations performed by the plurality of comparator circuits.

Abstract: A method and apparatus are provided. A radar signal comprising first identity information is received. Information on a non-radar channel comprising second identity information is received. It is determined that the radar signal and the information on the non-radar channel are sent from a first sender when the first and second identity information correspond.

Abstract: A method, system and device are disclosed for determining safety conflicts in redundant subsystems of autonomous vehicles. Each redundant subsystem calculates a world model or path plan, including locations, dimensions, and orientations of moving and stationary objects, as well as projected travel paths for moving objects in the future. The travel paths and projected future world models are subsequently compared using a geometric overlay operation. If at future time moments the projected world models match within predefined margins, the comparison results in a match. In case of a mismatch at a given future moment between projected world models, a determination is made as to whether the autonomous vehicle and all road users in this future moment are safe from collision or driving off the drivable space or road based on a geometric overlay operation.

Abstract: A method is carried out on a device capable of utilizing a high efficiency wireless local area network (HEW) communication protocol and a legacy communication protocol, and includes wirelessly receiving a communication frame; when the measured energy level of the frame exceeds a static clear channel assessment (CCA) energy level, identifying the BSS to which the frame corresponds, wherein identifying the BSS to which the frame corresponds comprises utilizing a BSS identifier included in the frame when the frame is an HEW frame or utilizing a MAC address included in the frame when the frame is a legacy frame; when the frame corresponds to the same BSS as the device, processing the frame utilizing the static CCA energy level; and when the frame corresponds to an overlapping OBSS, processing the frame utilizing a dynamic CCA energy level.

Abstract: A Doherty power amplifier includes input circuitry that provides input signals to asymmetric carrier and peaking amplifiers (e.g., a peaking-to-carrier size ratio, ? is greater than 1.15) with an absolute value of an input phase offset between 15 degrees and 165 degrees or between 195 degrees and 345 degrees. Carrier and peaking amplifier output signals are combined at a combining node. A complex combining load matching circuit, which is connected to the combining node, provides a complex impedance, ZL, with a non-zero reactive portion, xn. The output circuit between the peaking amplifier and the combining node has an electrical length of 0 or n*180 degrees (n=an integer value). The output circuit between the carrier amplifier and the combining node has an electrical length, ?x, where a difference between the electrical lengths of the peaking output circuit and the carrier output circuit is equal to the input phase offset.