Abstract: Systems, methods, and apparatuses are disclosed herein for aligning HE-LTFs corresponding to a plurality of users by determining a respective number of spatial streams corresponding to each user, determining a highest respective number of spatial streams of the spatial streams, and setting an alignment number of HE-LTF symbols to be equal to or larger than the highest respective number of spatial streams. For each respective user, a respective matrix of HE-LTF symbols corresponding to the respective number of spatial streams of the respective user is selected, and it is determined whether the respective matrix of HE-LTF symbols has fewer symbols than the alignment number. In response to determining that the respective matrix of HE-LTF symbols has fewer symbols than the alignment number, padding symbols may be added to the respective matrix to yield a number of HE-LTF symbols in the respective matrix that corresponds to the alignment number.

Abstract: A controller for a FMCW radar system configured to: provide for emission by the FMCW radar system of a plurality of consecutive frequency modulated detection signals for detection and ranging, each of the frequency modulated detection signals varying between an initial frequency and a final frequency over a period of time extending from a start time to an end time; wherein at least one of said consecutive frequency modulated detection signals is provided with an offset to one or more of; the start time of the detection signal relative to a predetermined start time schedule; the end time of the detection signal relative to a predetermined end time schedule; the initial frequency of the detection signal relative to a predetermined initial frequency schedule; and the final frequency of the detection signal relative to a predetermined final frequency schedule; the offset based on a random value.

Abstract: A packaged semiconductor device has a conductive film that covers a first major surface and surrounding side surfaces of an integrated circuit die. The conductive film provides five-sided shielding of the integrated circuit die. A metal heat sink may be attached to an exposed major surface of the conductive film for dissipating heat generated by the die.

Abstract: A MEMS device includes a first inertial mass system having first drive and sense masses elastically coupled to one another and a second inertial mass system having second drive and sense masses elastically coupled to one another. The first and second drive masses undergo antiphase drive motion along a first axis parallel to the surface of the substrate. First and second sense springs anchor and suspend first and second sense masses spaced apart from the surface of the substrate. The first and second sense springs enable antiphase sense motion of the first and second sense masses along a second axis parallel to the surface in response to an angular rotation about a third axis perpendicular to the surface. The first and second sense springs further enable in-phase sense motion of the first and second sense masses along the second axis in response to a linear acceleration along the second axis.

Abstract: A method is provided for shuffling an order of a plurality of data blocks. In the method, a random number is generated, the random number corresponding to an index for a data block of the plurality of data blocks, where each data block of the plurality of data blocks has an index that uniquely identifies each data block of the plurality of data blocks. The increment function with a parameter is applied to the random number to generate a new index, the new index corresponds to a data block of the plurality of data blocks. The data block corresponding to the new index is selected as the next data block of a reordering of the plurality of data blocks. The method is iterated until the reordering of the plurality of data blocks is complete.

Abstract: A method of manufacturing a packaged semiconductor device includes forming an assembly by placing a semiconductor die over a substrate with a die attach material between the semiconductor die and the substrate. A conformal structure which includes a pressure transmissive material contacts at least a portion of a top surface of the semiconductor die. A pressure is applied to the conformal structure and in turn, the pressure is transmitted to the top surface of the semiconductor die by the pressure transmissive material. While the pressure is applied, concurrently encapsulating the assembly with a molding compound and exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter.

Abstract: A free running oscillator (FRO) includes a reference current generator, a current converter, and first and second oscillator cores. The reference current generator generates a first current. The current converter generates a second current based on the first current. The first oscillator core generates a clock signal at a first frequency based on a first value of the second current. The second oscillator core generates a clock signal at a second frequency based on a second value of the second current. The second frequency may be lower than the first frequency, and the second value of the second current lower than the first value of the second current.

Abstract: A first communication device allocates respective frequency sub-channels for subsequent orthogonal frequency division multiple access (OFDMA) communications with two or more second communication devices, including allocating a first frequency sub-channel, a second frequency sub-channel, and a third frequency sub-channel between the first frequency sub-channel and the second frequency sub-channel. The first communication device generates and transmits a first downlink OFDMA data unit configured to prompt the two or more second communication devices to transmit as part of a multi-user transmission that spans the first frequency sub-channel, the second frequency sub-channel, and the third frequency sub-channel. The first communication device receives an uplink OFDMA transmission and determines that the uplink OFDMA transmission did not include a transmission within the third frequency sub-channel.

Abstract: A method for reducing transistor sensitivity to shallow trench isolation defects (STI) includes filling a trench formed in a substrate of a semiconductor device, at least partially, with a first oxide, the trench defines an STI and includes a defect extending from the substrate. A mask defines a planar area within the isolation region including a first lateral distance between an edge of the mask and an edge of the isolation region. The first oxide is at least partially removed beneath the planar area with an oxide etch to expose a top portion of the defect. The top portion of the defect is removed with a semiconductor etch. After removing the top portion of the defect, the trench is at least partially filled with a second oxide. A field plate of a split-gate transistor is formed over the STI.

Abstract: In accordance with a first aspect of the present disclosure, a method for providing a code pattern which is readable by a sensor is conceived, the method comprising: defining a plurality of coding positions as a subset of positions in a two-dimensional matrix; including in said subset a plurality of positions which are diagonally adjacent to each other; selectively creating coding marks, such as coding dots, at the coding positions. In accordance with a second aspect of the present disclosure, a corresponding code pattern is provided.

Abstract: A pipeline analog-to-digital converter (ADC) includes a hybrid multiplying digital-to-analog converter (MDAC) that includes multiple digital-to-analog converters (DACs), an amplifier, and a conversion circuit. The multiple DACs function in a pipelined manner such that each DAC receives an analog input signal in different cycles of a clock signal and generates a corresponding analog output signal. The amplifier amplifies each analog output signal to generate a corresponding amplified analog signal in different cycles of the clock signal. The conversion circuit successively approximates each analog output signal to generate multiple digital signals. Thus, a digital output signal of the pipeline ADC is generated based on the corresponding amplified analog signal and at least one of the multiple digital signals. The pipeline ADC utilizes one cycle for performing each of sampling, conversion, and amplification operations, which results into low power consumption by the pipeline ADC.

Abstract: An apparatus embodiment includes a voltage regulator circuit that provides a regulated voltage supply signal, logic state circuitry, test control circuitry, and a supply-signal monitoring circuit. The logic state circuitry includes logic modules that are reconfigured between application controlled self-test modes in which data is shifted through the logic module and while being powered from the regulated voltage supply signal. The test control circuitry operates the controlled self-test mode by causing a predetermined set of the data to shift through the logic modules and that causes the logic state circuitry to load the voltage regulator circuit by stressing the voltage regulator circuit. The supply-signal monitoring circuit monitors a quality parameter of the regulated voltage supply signal and provides an indication of characteristics of the regulated voltage supply signal which bear on a likelihood that the voltage regulator circuit is associated with defective circuitry.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method of operating an ESD protection device are described. In one embodiment, the ESD protection circuit is connected between a VDD rail and a VSS rail and includes an internal floating ESD rail located between the VDD rail and the VSS rail, I/O pins connected between the internal floating ESD rail and the VSS rail, ESD diodes corresponding to at least one I/O pin, an internal bias cell corresponding to an I/O pin and configured to short the corresponding I/O pin to the internal floating ESD rail when the I/O pin is pulled high, and an internal bias cell corresponding to a VDD pin of the VDD rail and configured to short the VDD rail to the internal floating ESD rail when the VDD pin is pulled high.

Abstract: A circuit to protect a USB connector from corrosion on its CC pins includes a first node coupled to a first power source or a first pull-down resistor, a second node coupled to the CC pins and a second power source, and a second pull-down resister coupled to the second node. A detection circuit compares the voltage at the first node with a first reference voltage. The detection circuit also compares the voltage at the second node with second and third reference voltages. A control logic circuit generates a corrosion detection signal in response to the voltage at the second node being less than the third reference voltage and greater than the second reference voltage when the voltage at the first node is greater than the first reference voltage.

Abstract: A radio frequency (RF) amplifier circuit includes a field effect transistor (FET) (e.g., a FET belonging to a III-V FET enhancement group), where the FET includes a gate terminal coupled to an RF input node. The circuit further includes a prematch and biasing network coupled between a bias voltage node and the RF input node. The prematch and biasing network includes a nonlinear gate current blocking device configured to block a current from flowing between the bias voltage node and the RF input node.

Abstract: One example discloses a near-field measuring device, including: a near-field antenna; a tuning circuit galvanically coupled to the near-field antenna and configured to set a resonant frequency and/or a quality factor of the measuring device; and a current sensor inductively coupled to the near-field antenna and configured to generate a signal in response to a current flowing through the galvanic coupling between the near-field antenna and the tuning circuit; wherein the signal represents a measurement of non-propagating quasi-static near-field signals received by the near-field antenna.

Abstract: The present application relates to a node for conducting measurements and signal analyses on a bus supporting multi-master access of a plurality of nodes or a transceiver of the node. The transceiver is configured to detect bus signals and to convert the detected bus signals into a bit stream. A protocol engine is arranged to receive the bit stream. The protocol engine transitions between states, which are indicative of at least an exclusive access phase, during which only one of the plurality of nodes is allowed to assert signals on the bus. A detector is configured to assert an enable indication for a period of time on detecting that the protocol engine is in a state indicative of the exclusive access phase. A diagnosis module is configured to conduct measurements in response to the asserted enable indication.

Abstract: A memory includes a row decoder that receives an address of a row to be read and an operand. The memory includes a memory array of bitcells that can be configured to store N-bit weight values in which N is an integer greater than one. The row decoder is configured to, for a multiplication mode read operation at the selected word line, selectively activate the selected word line based on a bit value of the received operand to selectively read an N-bit weight value based on a bit value of the operand. Such an operation may in some embodiments, perform a multiplication operation of the bit value of the operand and the N-bit weight value.

Abstract: A semiconductor device includes a semiconductor substrate configured to include a channel, a gate supported by the semiconductor substrate to control current flow through the channel, a first dielectric layer supported by the semiconductor substrate and including an opening in which the gate is disposed, and a second dielectric layer disposed between the first dielectric layer and a surface of the semiconductor substrate in a first area over the channel. The gate may be configured to include a lateral overhang that is separated from an upper surface of the first dielectric layer.

Abstract: The present disclosure relates to a bus device and a corresponding bus system. Furthermore, the present disclosure relates to a corresponding method of operating a bus device. In accordance with a first aspect of the present disclosure there is provided a bus device comprising a bus protocol controller with a transmit data output and a bus transceiver with a transmit data input coupled to the transmit data output of the bus protocol controller, wherein the bus protocol controller is configured to provide a serial bit stream designated for transmission through a bus via the transmit data output of the bus controller and via the transmit data input to the bus transceiver and to provide a switching signal within the serial bit stream, and wherein the bus transceiver is configured to switch between different operating modes in response to the switching signal.