Abstract: A method and receiver are provided. The receiver comprises a first delay buffer and redundant data removal block. The first delay buffer is configured to delay a first data stream carrying first content. The first data stream is comprised of a plurality of compressed data blocks. The redundant data removal block configured to for each compressed data block of the first data stream: identify redundant data in the compressed data block; remove the redundant data to provide a reduced compressed data block; and store the reduced compressed data block in the first delay buffer.

Abstract: The embodiments described herein provide systems and methods for digital correction in low intermediate frequency (IF) receivers. Specifically, the embodiments described herein use digital correction techniques that can correct for signal distortions in low IF receivers caused by I-Q imbalance, including both I-Q magnitude imbalance and I-Q phase imbalance. In general, the embodiments described herein are implemented to at least partially cancel an image of a blocking signal in the complex digital signal. Such a cancellation can be implemented to at least partially cancel an image of blocking signal where that image occurs at or near the intermediate frequency. In one embodiment, a corrector is implemented in a low RF receiver and is configured to receive a complex digital signal that includes an image of a blocking signal. Such a low RF receiver can further include a corrector controller to selectively enable the corrector.

Abstract: A method and apparatus are provided for controlling a sensorless multi-phase permanent magnet (PM) motor by sensing induced motor terminal voltages from the PM motor while the rotor is spinning, generating an input voltage vector signal from the plurality of induced motor terminal voltages, projecting the input voltage vector signal to a transformed voltage vector signal which does not include DC-offset components by using a Clarke transformation without a zero component that is applied to the input voltage vector signal, and estimating an initial rotor position of the rotor from the transformed voltage vector signal, wherein said sensing, projecting, and estimating are performed while a power converter for the sensorless multi-phase PM motor is disabled.

Abstract: A mechanism is provided by which a hardware filter on a border router of a wireless personal area network is not overloaded by increasing the probability that the hardware filter will capture all the nodes not on the corresponding WPAN. Network addresses for nodes within a subnet are allocated to have the same multicast address hash value in order to permit router multicast filtering to occur within hardware. Hardware filtering thereby relieves the router processor from performing filtering tasks, reducing resource consumption and decreasing the time used to perform filtering. Embodiments provide this functionality by assigning a unique multicast filter register value to each subnet within a network and allocating network addresses associated with that multicast filter register value through either DHCP or SLAAC address generation.

Abstract: There is disclosed a data processing device for executing an application, the data processing device comprising a processing unit for controlling access to at least one user interface comprised in the data processing device, and a secure element for facilitating secure execution of the application, wherein executing the application comprises receiving input data from and/or sending output data to the user interface, and wherein the secure element is arranged to cause the processing unit to restrict the access to the user interface during execution of the application. Furthermore, a corresponding method for executing an application and a corresponding computer program product are disclosed.

Abstract: An integrated circuit includes a pulse generator having at least one delay circuit with an input that receives a clock signal and an output that provides a delayed clock pulse. The delayed clock pulse has a width proportional to an amount of time required to maintain a magnitude of the clock signal. A pulse latch circuit includes a clock input coupled to receive the delayed clock pulse, a data input coupled to receive a data value, and a data output, wherein the pulse latch circuit outputs and holds the data value at the data output each time the delayed clock pulse is provided at the clock input, and the pulse latch circuit operates on a continuous voltage source that supplies power during power on and power off modes.

Abstract: Performing a temperature measurement operation includes a first phase and a second phase. The first phase includes providing a voltage indicative of a measured temperature to a first input of a comparator, providing a ramp signal to a second input of the comparator, and generating at an output of the comparator, pulses based on a comparison of the first input to the second input of the comparator. The second phase includes providing the voltage indicative of a measured temperature to the second input of the comparator, providing the ramp signal to the first input of the comparator, and generating at an output of the comparator, pulses based on a comparison of the first input to the second input of the comparator. Performing the temperature measurement operation also includes utilizing the pulses generated during the first and second phases to provide a digital indication of the measured temperature.

Abstract: Certain aspects of the disclosure are directed to methods and apparatuses of intrusion detection for integrated circuits. An example apparatus can include a wired communications bus configured and arranged to carry data and a plurality of integrated circuits. The plurality of integrated circuits can include a first integrated circuit configured and arranged to operate in a scan mode during which the first integrated circuit performs a scan test to detect one or more faults in circuitry of the plurality of integrated circuits. The plurality of integrated circuits can further include a second integrated circuit configured and arranged to operate in a mission mode and supervise data traffic by monitoring communications including data patterns and accesses on the wired communications bus. In response to identifying a suspected illegitimate access, the second integrated circuit can perform a security action to mitigate a suspect illegitimate action in the plurality of integrated circuits.

Abstract: Embodiments described herein provide a method for transmitting a wake-up radio signal to low power devices in a wireless local area network. At a wireless access point, data for transmission to one or more lower power wireless devices is received. A wake-up radio packet is generated, including a wake-up data frame destined for the one or more lower power wireless devices. The wake-up data frame is configured with: a type field indicative of a type of the wake-up data frame, and a first identifier field indicative of information corresponding to the one or more lower power wireless devices. The wake-up radio packet is transmitted to the one or more lower power wireless devices to turn on wireless receivers at the one or more low power wireless devices prior to initiating data transmission with the one or more lower power wireless devices.

Abstract: A method for simultaneously communicating with multiple communication devices in a wireless local area network is described. Multiple uplink data units are received that are simultaneously transmitted by multiple second communication devices. The multiple uplink data units include a management data unit and a traffic data unit. An acknowledgment data unit is generated to acknowledge receipt of the multiple data units. The acknowledgment data unit includes (i) an indication that indicates that the acknowledgment data unit is intended for the multiple second communication devices, and (ii) respective acknowledgment information fields for the multiple second communication devices. The respective acknowledgment information fields include a first acknowledgment information field for the management data unit and a second acknowledgment information field for the traffic data unit.

Abstract: A software only debug approach is provided that does not require special hardware in a target embedded system undergoing debug. Instead, already present DMA capabilities of the target system are utilized to transfer I/O operation parameters into a memory area accessible to both the target processor and a debugger executing on a host system. The debugger can thereby access and execute the I/O operations without program execution stopping on the target. A semihosting library is provided as a replacement for the standard C I/O library on the target. The semihosting library provides a range of equivalent functions to the standard C I/O API that program a DMA transfer to copy the I/O function parameters to an external memory area that is not otherwise being used by the target core processor. The external memory area is then accessed by a debug tool on the host computer.

Abstract: System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.

Abstract: In accordance with a first aspect of the present disclosure, a fingerprint sensing device is provided, comprising: a substrate; a fingerprint sensor placed on one side of the substrate; a coupling electrode placed on another side of the substrate, wherein said coupling electrode is arranged to provide a coupling capacitance between a surface of a finger and a circuit ground of said fingerprint sensor. In accordance with a second aspect of the present disclosure, a corresponding method of producing a fingerprint sensing device is conceived.

Abstract: A first communication device prompts a plurality of second communication devices to transmit, during a contiguous time period reserved for a range measurement exchange, respective first null data packets (NDPs) at respective times. The first communication device receives first NDPs from at least some of the second communication devices during the contiguous time period, and transmits one or more second NDPs to the plurality of second communication devices. The first communication device uses reception of the first NDPs and transmission of the one or more second NDPs to determine respective ranges between the first communication device and respective second communication devices.

Abstract: A copper lead frame used in the assembly of a semiconductor device includes a die flag and lead fingers extending away from the die flag. Each lead finger has a proximal end near the die flag and a distal end further away from the die flag. Metal plating is formed on the lead fingers, where first lead fingers have the metal plating on their proximal ends and second lead fingers have the metal plating on their distal ends. The first and second lead fingers are arranged alternately around the die flag.

Abstract: A RFID tag (1) for communicating with an external reader comprises: two antenna connections (LA, LB) for connecting the RFID tag (1) to an antenna (10), an active receiver switch circuit (5) for receiving two input sinusoidal signals from the two antenna connections (LA, LB) and generating a rectified waveform signal (8), a modulation detection circuit (12) for receiving two input sinusoidal signals from the two antenna connections (LA, LB) and generating a first demodulation signal (13) related to a 10% amplitude modulation of a RF field for communication between the reader and the RFID tag (1) and a second demodulation signal (14) related to a 100% amplitude modulation of a RF field for communication between the reader and the RFID tag (1).

Abstract: An Ultra-Wideband (UWB) wireless communication device includes a scanning circuit, an ordering circuit, and a selecting circuit. The scanning circuit is configured for scanning at least a channel supported by the communication device for detecting a plurality of patterns of a UWB frame format. The ordering circuit is configured for ordering the plurality of patterns in a patterns list according to a predefined quality parameter. The selecting circuit is configured for selecting at least one of the patterns in the list to start an Ultra Wideband (UWB) wireless communications.

Abstract: Aspects are directed toward a data-communication approach using an arrangement of node-node communication according to a protocol involving layered routing of payload as might be similar to layered-based communication-protocol standards used in automotive applications. A particular payload is conveyed between nodes via a protocol having a data link layer and a network layer, the latter being used to indicate to which node(s) the payload is to be routed. For compatibility with standard(s), the protocol accommodates transfer of data between nodes by permitting for use of both the data link and network layers. In some implementations, to increase efficiency and processing overhead for payload transmissions, the protocol does not require use of the network layer to indicate where to transfer the payload.

Abstract: A communication device sets a first channel access timer to a first duration in which at least a first portion of a communication channel is expected to be busy, the first timer corresponding to a first one of a plurality of component channels of the communication channel. The communication device also sets a second channel access timer to a second duration in which at least a second portion of the communication channel is expected to be busy, the second timer corresponding to a second one of the plurality of component channels. The communication device counts down the first timer and the second timer. When at least one of the first timer and the second timer reaches zero, the communication device determines whether one or more of the component channels are idle, and transmits at least one signal in at least one of the component channels determined to be idle.

Abstract: It is described a method for protecting unauthorized data access from a memory area of a computing system operable in a first operating mode and in at least one second operating mode, the method comprising: requesting, in the first operating mode, payload data stored in a memory area from a memory controller; retrieving, by the memory controller, the payload data from the memory area; retrieving, by the memory controller, second check data associated with the payload data from the memory area; failing by checking the payload data using the second check data according to a first check mechanism, while a check of the payload data using the second check data according to a second check mechanism passes.