Abstract: A power controller, including power stages configured to receive input power and charge an inductor, the power stages including output power stages configured to output a first voltage and a second voltage, and feedback circuits to determine error signals of the first voltage and second voltage, a first loop configured to determine an amount of energy to be stored in the inductor using the error signals, and a second loop configured to determine a discharge of the inductor between the first voltage and the second voltage, wherein the second loop determines a moving average of at least one transition point between powering the first voltage and the second voltage.

Abstract: A communication device receives a physical layer (PHY) data unit via a communication channel, and analyzes i) a length value in a field in a legacy portion of a PHY preamble of the PHY data unit, and ii) a phase of modulation of an orthogonal frequency division modulation (OFDM) symbol in a non-legacy portion of the PHY preamble. The communication device determines a format of the received PHY data unit corresponding to the analysis of i) the length value and ii) the phase of modulation of the OFDM symbol in the non-legacy portion of the PHY preamble, where the determined format is from a set of multiple PHY formats defined by a communication protocol. The communication device then processes the received PHY data unit according to the determined format.

Abstract: A clock generator includes an oscillator that generates a clock signal as an output of the clock generator, where the frequency of the clock signal is dependent on a bias current. A feedback circuit receives the clock signal and generates a feedback signal indicative of a frequency of the clock signal. A voltage detector generates a charged voltage using the feedback signal, compares a source voltage with the charged voltage, and generates a detection signal indicative of the comparison between the source voltage and the charged voltage. A control voltage generator generates a control voltage using the detection signal. The bias current is generated by a bias current source using the control voltage.

Abstract: A controller for operably coupling a drive unit to a host unit in a serial advanced technology attachment (SATA) system is described. The controller comprises a hardware processor arranged to: receive a plurality of SATA data frames; identify a first primitive sequence in at least one of the plurality of SATA data frames that adversely affects a performance of the SATA system; and replace the identified first primitive sequence with a second primitive sequence in response thereto.

Abstract: A word line regulator provides a write word line voltage for an asserted word line and includes a write replica circuit, a reference current path, and a regulator circuit. The write replica circuit is a replica of a write path for writing from a low to high resistance value of a resistive memory element of a memory cell. The word line regulator regulates the word line voltage at a value during the write operation of a low to high resistance value such that a select transistor of the memory cell is used as a source follower to regulate a first node of a resistive element of the memory cell being written. The first node is at a higher write voltage than a second node of the resistive element during the write operation, and the first node is located in a write path between the select transistor and the second node.

Abstract: A method for dynamic calibration of current sense for switching converters includes biasing a reference transistor with a Zero Temperature Coefficient current source, and a respective gate of each of the reference transistor and a power transistor with a gate voltage. The reference transistor and the power transistor each comprise a matching temperature coefficient. A reference voltage sensed across the reference transistor is multiplied by a gain, thereby generating a first calibration voltage, wherein the gain is determined by a gain coefficient. A transistor voltage sensed across the power transistor is multiplied by the gain, thereby generating a second calibration voltage. The first calibration voltage is compared to a target voltage to generate an error voltage. The gain coefficient is determined with an Analog to Digital Converter in response to the error voltage, thereby minimizing a difference between the target voltage and each of the calibration voltages.

Abstract: An input protection circuit (200) and associated method are disclosed for protecting a circuit input (VINP) from positive and negative overvoltages at an input voltage (VIN) with a high-voltage PMOSFET (P1) having a gate, a drain connected across a zener diode (ZD1) to the gate, and a source connected to receive an input voltage; a blocking FET (N1) having a gate connected to a power supply voltage, a drain connected across a zener diode (ZD2) to the power supply voltage, and a source connected to the gate of the high-voltage PMOSFET; a high-voltage NMOSFET (N3) having a gate connected to the power supply voltage, a source providing the protected output voltage and connected across a zener diode (ZD3) to the gate, and a drain connected to a source follower node and a level shifter circuit (214) connected between the drain of the high-voltage PMOSFET and the source follower node.

Abstract: An apparatus, a method, and an integrated circuit for a providing a temperature-compensated Zener reference are disclosed. In accordance with at least one embodiment, the apparatus comprises a proportional-to-absolute-temperature (PTAT) current source; a complementary-to-absolute-temperature (CTAT) current source; and a Zener diode, with the PTAT current source coupled to a first Zener diode terminal of the Zener diode, the CTAT current source coupled to the first Zener diode terminal of the Zener diode, and the PTAT current source providing a PTAT current and the CTAT current source providing a CTAT current, wherein the PTAT current and the CTAT current are combined for provide a temperature-compensated bias current.

Abstract: The present disclosure describes methods and apparatuses for improved target wake time (TWT) operations in wireless networks. In some aspects, an access point transmits a trigger frame to stations of a TWT session during a TWT service period. Responsive to the trigger frame, the access point receives respective uplink frames transmitted by the stations. The access point then transmits a multi-block acknowledgment (M-BA) frame with a per association identifier traffic identifier (per AID TID) field configured to indicate whether one or more of the stations are permitted to enter a low-power state before an end of the TWT service period. By so doing, stations that are typically unable to interpret a more data field of the M-BA frame can determine based on the per AID TID if they are permitted to enter the low-power state and conserve power during a remainder of the TWT service period.

Abstract: A first communication device generates and transmits a first physical layer (PHY) data unit as part of a hybrid automatic repeat request (HARQ) session, the first PHY data unit having a first plurality of media access control (MAC) protocol data units (MPDUs) including a first MPDU. The first communication device determines that a second communication device did not acknowledge successfully receiving the first MPDU. The first communication device generates and transmits a second PHY data unit as part of the HARQ session, the second PHY data unit having a second plurality of MPDUs, the second plurality of MPDUs including the first MPDU.

Abstract: A radio receiver is disclosed. The radio receiver includes an analog tuner and a baseband processor to provide radio functions. The baseband processor is coupled to the analog tuner. The radio receiver further includes a memory, a controller coupled to the analog tuner, the baseband processor and the memory. The controller is configured to perform an operation, the operation includes causing the analog tuner to analyze a selected FM frequency to determine if the selected FM frequency is associated with a digital radio mondiale (DRM) plus station by first coarsely determine if the selected FM frequency may be associated with a DRM plus station and if coarse determination fails, marking the FM frequency as not being associated with a DRM plus station, wherein if the coarse determination is successful, retrying a selected number of times to continue to determine if the selected FM frequency is associated with a DRM plus station.

Abstract: A semiconductor sensor device includes a lead frame flag having a vent hole, an interposer mounted on the flag and having a vent hole in fluid communication with the vent hole of the flag, and a sensor die having an active region. The sensor die is mounted on and electrically connected to the interposer in a flip-chip manner such that the vent hole of the interposer is in fluid communication with the active region of the sensor die. Bond wires electrically connect the interposer to one or more other components of the device. A molding compound covers the sensor die, the interposer, and the bond wires. The sensor die may be a pressure-sensing (P-cell) die, and the device may also include a micro-controller unit (MCU) die and an acceleration-sensing (G-cell) die, for tire pressure monitoring applications.

Abstract: Embodiments of a method, a device and a computer-readable storage medium are disclosed. In an embodiment, a method for operating a Controller Area Network (CAN) device involves detecting a transition of a CAN transceiver of the CAN device from a dominant state to a recessive state and in response to detecting a transition of the CAN transceiver from the dominant state to the recessive state, controlling an output impedance of the CAN transceiver to be within a predefined range of an impedance value at the dominant state while a differential driver voltage on a CAN bus connected to the CAN transceiver decreases to a predefined voltage.

Abstract: A reconfigurable radar unit is described that includes: a millimetre wave (mmW) transceiver (Tx/Rx) circuit; a mixed analog and baseband integrated circuit; and a signal processor circuit. The mmW Tx/Rx circuit and mixed analog and baseband integrated circuit and signal processor circuit are configured to support a plurality of radar operational modes. a radar sensitivity monitor and architecture reconfiguration control unit (260) is coupled to the signal processor circuit and is configured to monitor a radar performance and, in response thereto, initiate a change in the radar operational mode. In this manner, a large number of radar operational modes is supported and can be dynamically adopted by the reconfigurable radar unit dependent upon any prevailing radar performance condition.

Abstract: A press-fit semiconductor device includes a lead frame having a die pad, leads with inner and outer lead ends, and a press-fit lead. The press-fit lead has a circular section between an outer lead end and an inner lead end, and the circular section has a central hole that is sized and shaped to receive a press-fit connection pin. A die is attached to the die pad and electrically connected to the inner lead ends of the leads and the inner lead end of the press-fit lead. The die, electrical connections and inner lead ends are covered with an encapsulant that forms a housing. The outer lead ends of the leads extend beyond the housing. The housing has a hole extending therethrough that is aligned with the center hole of the press-fit lead, so that a press-fit connection pin can be pushed through the hole to connect the device to a circuit board.

Abstract: A wireless communication unit (100) is described that comprises: at least one receiver configured to receive a radio frequency signal on at least one receiver channel (262, 264, 266, 268) and comprising a plurality of receiver circuits; at least one interference detection circuit (244, 248, 252) coupled to an output of at least one of the plurality of receiver circuits and configured to detect a saturation event of a signal output from the at least one of the plurality of receiver circuits; and a controller (114) configured to identify interference in a received signal.

Abstract: Various embodiments relate to a method and apparatus for embedding an operating system in a smart card product, which is certified and which derives multiple variants from the operating system, the method including the steps of certifying, a target of evaluation, the target of evaluation including an OS core mask and a plurality of components which includes OS components and plugin placeholders, building, by an image builder tool, romized content and runtime content including at least one of the plurality of components and customizing which of the plurality of components to include on the smart card product.

Abstract: A method for operating a first near field communication, NFC, device, wherein the NFC device comprises an NFC interface and a memory, the method comprising: i) receiving a request for a service from a second NFC device at the NFC interface, ii) allocating a first information from a first memory unit of the memory that is configured to take part in providing the service, iii) allocating a second information from a second memory unit that is not configured to take part in providing the service, and transferring the second information from the second memory unit to the first memory unit, hereby iv) transferring at least a part of the first information and/or at least a part of the second information virtually beyond the first memory unit, v) combining the first information and the second information into a message, and vi) providing the message to the second NFC device as a response to the request.

Abstract: An analog-to-digital converter (ADC) and a method are disclosed. The ADC includes dithering circuitry. The dithering circuitry includes a signal level detector, a dither amplitude controller, a random code generator, and a dither digital-to-analog converter (DAC). The signal level detector receives the analog input signal and provides amplitude level information associated with the analog input signal. The dither amplitude controller receives the amplitude level information from the signal level detector, and provides a control signal. The dither amplitude controller varies the control signal based on the amplitude level information. The dither DAC receives the control signal from the dither amplitude controller and a pseudo-noise (PN) signal from the random code generator, and provides the dither signal based on the control signal. The dither signal varies based on an amplitude level of the analog input signal.

Abstract: The present application relates to a transceiver, TX/RX PHY, and a method of operating the TX/RX PHY arranged for bi-directional data communication of a node with a counterpart node connected to in a point-to-point network using differential mode signaling over a single twisted-pair cable. A TX adjustment component is arranged in a TX path of the TX/RX PHY and configured to adjust a TX data communication signal generated by the TX/RX PHY for transmittal to the counterpart node. The TX adjustment component is further configured to accept information about a common mode signal detected on the single twisted-pair cable and to adjust the TX data communication signal to at least weaken the common mode signal occurring at the counterpart node in response to transmitting the TX data communication signal.