Abstract: A method for providing an authenticated update in a distributed network is provided. The distributed network has a plurality of nodes coupled to a serial bus. The method begins with transmitting a credential from an external device to a first node. The update data and an authentication code are provided to a processor of a second node from the external device. The processor of the second node provides the update data and the authentication code to the transceiver of the second node. The authenticated update is finalized by the processor of the second node. The authenticated update is closed by the transceiver of the first node. The credential of the authenticated update is provided to the transceiver of the second node. The transceiver of the second node verifies the update data using the credential and the authentication code. After being verified, the authenticated update data is stored.

Abstract: A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.

Abstract: A white-box system and method for producing a digital signature of a message m, including: a white-box implementation of a symmetric cipher configured to produce a deterministic nonce value by encrypting the message m using a secret key; and a digital signature algorithm configured to produce a digital signature of the message m based upon the deterministic nonce, the message m, and a secret signing key.

Abstract: A distributed aperture bi-static radar system, apparatus, architecture, and method is provided for coherently combining physically distributed radars to jointly produce target scene information in a coherent fashion by alternately selecting first and second small aperture devices to operate as the master unit so that radar signals are sequentially transmitted from every transmit antenna in the first and second small aperture devices, thereby enabling the radar control processing unit to coherently combine mono-static and bi-static virtual array apertures from the first and second small aperture radar devices to construct an extended bi-static MIMO virtual army aperture that is larger than the bi-static MIMO virtual array apertures produced by the first and second small aperture radar devices.

Abstract: A distributed radar system, apparatus, architecture, and method is provided for coherently combining physically distributed radars to jointly produce target scene information in a coherent fashion without sharing a common local oscillator (LO) reference by configuring a first (slave) radar to apply fast and slow time processing steps to target returns generated from a second (master) radar, to compute an estimated frequency offset and an estimated phase offset between the first and second radars based on information derived from the fast and slow time processing steps, and to apply the estimated frequency offset and estimated phase offset to generate a bi-static virtual array aperture at the first radar that is coherent in frequency and phase with a mono-static virtual array aperture generated at the second radar, thereby achieving better sensitivity, finer angular resolution, and low false detection rate.

Abstract: A radar system, apparatus, architecture, and method are provided for generating a mono-static virtual array aperture by using a radar control processing unit to construct a mono-static MIMO virtual array aperture from radar signals transmitted orthogonally from transmit antennas and received at each receive antennas, and to construct a mono-static MIMO forward difference virtual array aperture by performing forward difference co-array processing on the mono-static MIMO virtual array aperture to fill in holes in the mono-static MIMO virtual array aperture, thereby mitigating or suppressing spurious sidelobes caused by gaps or holes in the mono-static MIMO virtual array aperture.

Abstract: A radio frequency (RF) heating and defrosting apparatus may include an electrode which, when supplied with RF signal energy, may responsively radiate electromagnetic energy into a cavity of the RF heating and defrosting apparatus. This radiated electromagnetic energy may cause a thermal increase of a load in the cavity. A capacitor may be formed from a portion of the electrode and a conductive plate disposed adjacent to the electrode. The conductive plate may be coupled to a ground reference structure. Dielectric material(s) having a low dielectric constant may be disposed directly between the electrode and the conductive plate.

Abstract: Methods for producing high thermal performance microelectronic modules containing sinter-bonded heat dissipation structures. In one embodiment, the method includes embedding a sinter-bonded heat dissipation structure in a module substrate. The step of embedding may entail applying a sinter precursor material containing metal particles into a cavity provided in the module substrate, and subsequently sintering the sinter precursor material at a maximum processing temperature less than a melt point of the metal particles to produce a sintered metal body bonded to the module substrate. A microelectronic device and a heatsink are then attached to the module substrate before, after, or concurrent with sintering such that the heatsink is thermally coupled to the microelectronic device through the sinter-bonded heat dissipation structure. In certain embodiments, the microelectronic device may be bonded to the module substrate at a location overlying the thermally-conductive structure.

Abstract: A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.

Abstract: A duty cycle correction circuit includes a duty cycle adjuster that is configured to receive first and second differential input signals having first and second duty cycles, respectively, that are distorted with respect to a reference duty cycle. The duty cycle adjuster is further configured to iteratively adjust the first and second duty cycles to generate first and second differential output signals having third and fourth duty cycles that are within a predefined range of the reference duty cycle, respectively. During each iteration, the duty cycle adjuster adjusts the first and second duty cycles based on correction bits that are generated based on a duty cycle detection signal that indicates whether the third duty cycle is greater than or less than the fourth duty cycle, and a lock signal that is activated when the duty cycle detection signal toggles from one logic state to another.

Abstract: A processing module for a receiver device is disclosed. The processing module is configured to provide for processing of a signal received by the receiver device from a transmitter device. The signal includes a secure training sequence divided into a plurality of time spaced blocks. The secure training sequence incoudes a non-repeating pattern of symbols. The processing module is configured to, based on a first phase marker in the first block and a second phase marker in the second block defining a phase difference of the signal between the first and second antennas and a known spacing of the first antenna relative to the second antenna, determine an angle of arrival of the signal relative to the receiver device.

Abstract: A circuit for generating a bias voltage for a terminating end capacitor in a controller area network (CAN) bus having a CANH and a CANL terminals is disclosed. The circuit includes a configurable voltage source, a controller to generate a control signal to operate the configurable voltage source, a CANH error detector and a CANL error detector. The CANH error detector and the CANL error detector are configured to provide inputs to the controller. The controller is configured to generate the control signal based on the outputs of the CANH error detector and the CANL error detector. The configurable voltage source is configured to output a bias voltage based on the control signal.

Abstract: The embodiments described herein provide radio frequency (RF) amplifiers, and in some embodiments provide amplifiers that can be used in high power RF applications. Specifically, the amplifiers described herein may be implemented with multiple resonant circuits to provide class F and inverse class F amplifiers and methods of operation. In general, the resonant circuits are implemented inside a device package with a transistor die to provide high efficiency amplification for a variety of applications.

Abstract: A DC-DC converter selectively operates in at least a first burst mode having at least one first-mode charge cycle with a first-mode charging phase followed by a first-mode discharging phase or a second burst mode having at least one second-mode charge cycle with a second-mode charging phase followed by a second-mode discharging phase. A first-mode charging phase is terminated when an inductor current flowing through the inductance reaches a first-mode peak-current threshold, and a first-mode discharging phase is terminated when the inductor current reaches a first-mode valley-current threshold.

Abstract: Embodiments are provided herein for a radar system and a method for determining true velocity, which includes: obtaining a radial velocity component that corresponds to a target object, based on sensor data detected by a radar sensor on a vehicle; obtaining a true velocity magnitude of the target object from a communication protocol; and calculating a true velocity angle of direction of the target object based on a trigonometric relationship established between the radial velocity component and the true velocity vector.

Abstract: This specification discloses methods for integrating a SiGe-based HBT (heterojunction bipolar transistor) and a Si-based BJT (bipolar junction transistor) together in a single manufacturing process that does not add a lot of process complexity, and an integrated circuit that can be fabricated utilizing such a streamlined manufacturing process. In some embodiments, such an integrated circuit can enjoy both the benefits of a higher RF (radio frequency) performance for the SiGe HBT and a lower leakage current for the Si-based BJT. In some embodiments, such an integrated circuit can be applied to an ESD (electrostatic discharge) clamp circuit, in order to achieve a lower, or no, yield-loss.

Abstract: Data from a communications channel is decoded by receiving data bits corresponding to encoded data, determining a set of data representations from the data bits, distributing the set of data representations into bins across a dynamic range to generate a distribution of the data representations, assigning a respective intermediate scale factor to each bin, deriving a set of moments from the intermediate scale factors, combining the moments into a scaling factor, scaling the data representations by the scaling factor, and sending the scaled data representations to a decoder. The data representations may be a histogram or cumulative distribution function of log-likelihood ratios (LLRs) or values based on channel estimates. In an iterative implementation performed until a stopping condition is met, the data representations may be scaled down on later iterations to avoid saturation. A correction factor may be applied to update the scaling factor for later data bits.

Abstract: Digital testing is performed on an integrated circuit while radiation upsets are induced at locations of the integrated circuit. For each digital test, a determination is made as to whether there is a variation in the output of the digital test from an expected output of the digital test. If there is variation, a time of the variation is indicated. In one example, a location of a defect in the digital circuit can be determined from the times of the variations. In other embodiments, a mapping of the digital circuit can be made from the times.

Abstract: A method includes receiving a first signal at an input of a device driver included at an electronic device, the first signal representing first information. A second signal representing the first information is provided at an output of the device driver. The output of the device driver, under normal operating conditions, is coupled to an output terminal of the electronic device. A third signal at the output terminal is received at feedback circuitry of the electronic device. The feedback circuitry identifies a fault at the output terminal based on the third signal and the first signal.

Abstract: Aspects of the present disclosure are directed to facilitating communications to respective circuit nodes in a manner that may also be useful for mitigating undesirable signal attenuation. As may be implemented in accordance with one or more embodiments, switchable isolation circuits, presented by at least one transformer and switch, are utilized to isolate adjacent data processing nodes on a bus in which each data processing node includes logic circuitry and processes signal therein. For each of the switchable isolation circuits, switching circuitry operates to mitigate communication propagation over the differential bus between adjacent data processing nodes, by switching the switchable isolation circuit for providing isolation. This approach may be utilized, for example, to assign sequential identification to daisy-chained circuit nodes upon start-up or reset, for use in addressing each node directly for further communication therewith.