Abstract: A network node and a method of updating and distributing secret keys in a distributed network is suggested. The network comprises a plurality of nodes connected to a shared medium of the distributed network. Each node of the plurality of nodes is member of at least one group of a plurality of groups. Each group is associated with a secret group key. Each node of the plurality of nodes stores only the one or more secret group keys, of which it is member. A first node of the plurality of nodes generates an authenticated update key request. The authenticated update key request comprises an indication of a membership, of which the first node is member. The first node broadcasts the authenticated update key request on the shared medium of the distributed network. Each remaining nodes of the plurality of nodes receives the authenticated key update.

Abstract: A lead frame for assembling a smart card is formed with a substrate having first and second opposing major surfaces. A die receiving area is formed in the first major surface of the substrate and surrounded by conductive vias. A conductive coating is formed on the second major surface of the substrate and patterned to form electrical contact pads over the conductive vias. A conductive trace is formed on the first major surface of the substrate. The conductive trace extends between at least two adjacent vias and partially surrounds the at least two adjacent conductive vias, thereby forming a gap in the portion of the trace that surrounds the vias. An electrical connection between an integrated circuit chip and the conductive via extends over the gap. The gap prevents the electrical connection from inadvertently contacting the conductive trace.

Abstract: Embodiments are directed to apparatuses and methods involving a phase-error tracking circuit. An example apparatus includes a divide-by phase locked loop (PLL) circuit to generate a continuous wave signal that sweeps over a frequency range in response to a divider feedback signal and to a reference signal. The apparatus further includes the phase-error tracking circuit defining a phase-error window in which the divide-by PLL circuit is to lock based on a slope associated with a rate of change of the frequency range, and indicating whether a phase error between the divider feedback signal and the reference signal coincides with the phase-error window.

Abstract: A first communication device transmits a first packet that includes a wakeup request packet configured to prompt a wakeup radio at a second communication device to prompt a network interface device of the second communication device to transition from a low power state to an active state. The first communication device measures a delay period after an end of transmission of the first packet. The delay period corresponds to a time required for the network interface device of the second communication device to transition from the low power state to the active state. After at least the delay period, the first communication device transmits the second packet.

Abstract: A MEMS device includes first, second, third, and fourth sense masses spaced apart from a surface of a substrate. A first drive coupler interconnects the first sense mass with a first actuator, a second drive coupler interconnects the second sense mass with a second actuator, a third drive coupler interconnects the third sense mass with a third actuator, and a fourth drive coupler interconnects the fourth sense mass with a fourth actuator. Each of the drive couplers includes a torsion bar having a length aligned parallel to an outer sidewall of an adjacent sense mass and first and second coupling links coupled to opposing first and second ends of the torsion bar. The first and second coupling links couple an adjacent one of the first, second, third, and fourth sense masses with a corresponding one of the first, second, third, and fourth actuators.

Abstract: A multiple-stage amplifier includes a driver stage die and a final stage die. The driver stage die includes a first type of semiconductor substrate (e.g., a silicon substrate), a first transistor, and an integrated portion of an interstage impedance matching circuit. A control terminal of the first transistor is electrically coupled to an RF signal input terminal of the driver stage die, and the integrated portion of the interstage impedance matching circuit is electrically coupled between a current-carrying terminal of the first transistor and an RF signal output terminal of the driver stage die. The second die includes a III-V semiconductor substrate (e.g., a GaN substrate) and a second transistor. A connection, which is a non-integrated portion of the interstage impedance matching circuit, is electrically coupled between the RF signal output terminal of the driver stage die and an RF signal input terminal of the final stage die.

Abstract: A wireless network includes a base station and a user equipment. The base station is configured to wirelessly transmit radio frequency (RF) signaling representing synchronization signal block (SSB) burst comprising a set of SSBs, each SSB associated with a different beam transmitted by the base station and having a corresponding index value representing a position of the SSB in the SSB burst. The user equipment is configured to detect an SSB of the SSB burst and to identify an index value of the SSB by iteratively performing a decoding process for a physical broadcast channel (PBCH) of the SSB, each performed iteration using a different index values selected from a prioritized ordering of the set of index values.

Abstract: An access point generates a trigger frame to trigger an uplink multi-user (MU) transmission by multiple client stations. The access point generates the trigger frame to include a common information field and multiple per-station information fields. The access point generates the common information field to include (i) a subfield that indicates a bandwidth of the uplink MU transmission, and (ii) information that indicates a guard interval and a long training field (LTF) mode to be used by the multiple client stations for the uplink MU transmission, and generates each per-station field to include respective frequency allocation information that indicates respective frequency resources to be used by the respective client station for the uplink MU transmission. The access point transmits the trigger frame to the multiple client stations to trigger the uplink MU transmission by the multiple client stations.

Abstract: A Sigma-Delta analog to digital converter (ADC) is described. The Sigma-Delta ADC includes a series arrangement of a gain tracker, a first discrete-time integrator stage and a quantizer between an ADC input and an ADC output. The Sigma-Delta ADC includes a digital to analog converter (DAC) having a DAC input and a DAC output connected to the gain tracker. The Sigma-Delta analog to digital converter includes a controller having a control input connected to the quantizer output. The controller provides a digital input to the DAC input and provides a gain control signal to the gain tracker.

Abstract: A transmission system comprising: an output-terminal configured to provide an output-signal; a phase-shift oscillator comprising a plurality of phase-shifters, each configured to provide one of a plurality of phase-shifted-signals; and a controller configured to provide a selected one of the phase-shifted-signals to the output-signal as a transition in the output-signal, at an instant in time that is based on one or more of the plurality of phase-shifted-signals.

Abstract: An A/D converter includes multiple bin comparators that compare an analog voltage to corresponding bin threshold voltages to provide output signals for providing corresponding comparison results. Some of the comparators includes enable inputs that selectively enable the output signal of the bin comparator to provide the corresponding comparison result based on a corresponding comparison result from at least one other bin comparator. The A/D convertor includes an encoder that utilizes the output signals to provide encoded bit values of the digital output. The A/D converter includes a bin selection circuit that utilizes the output signals to select a voltage level based on the output signals and provides the selected voltage level to a next stage of the A/D convertor. The next stage uses the selected voltage level and the analog voltage to provide at least one lessor bit of the digital output.

Abstract: A method includes, at a frequency shift keying (FSK) demodulator, determining a likelihood of a symbol having a first symbol value or a second symbol value, using the likelihood of the symbol to select either the first symbol value or the second symbol value for the symbol, the first symbol value or the second symbol value that is selected being a selected symbol value, selecting a frequency error from a first frequency error or a second frequency error, and using a down-mixer and the frequency error to correct a frequency drift associated with a future selected symbol value.

Abstract: An apparatus for determining one or more calibration values of an ADC is configured to receive a first reference signal and a second reference signal and apply to the ADC the following: over a first signal application period, a first ADC input signal including the first reference signal; over a second signal application period, a second ADC input signal having a substantially equal magnitude and an inverse polarity to the first ADC input signal; over a third signal application period, a third ADC input signal including the second reference signal; and over a fourth signal application period, a fourth ADC input signal having a substantially equal magnitude and an inverse polarity to the third ADC input signal. The apparatus is configured to determine the one or more calibration values based, at least in part, on an ADC output signal of the ADC over the four signal application periods.

Abstract: A voltage detection circuit including an input voltage stage configured to scale down an input voltage to produce a scaled down voltage, a gain loss stage configured to receive and adjust the scaled down voltage based on a determined gain or loss to be applied to the scaled down voltage, and a comparison circuit configured to determine if the input voltage is over or under a desired voltage value.

Abstract: This specification discloses methods and devices for limiting output current of a voltage regulator, in order to protect the voltage regulator against component overstress in case of output load current overloading. In some embodiments, a current limitation circuit acting on a reference input voltage of a voltage regulator can limit the maximum output load current of the voltage regulator. Once the current limitation circuit detects an over current load, the reference voltage is adjusted or decreased to limit the maximum output load current. Additionally, these methods and devices can be coupled easily with a slew rate control circuit to also limit the inrush current.

Abstract: A circuit includes a high voltage (HV) transistor having a first current electrode, a second current electrode, and a control electrode coupled to receive a control signal. The HV transistor is configured and arranged to be non-conductive when the control signal is at a first state and conductive when the control signal is at a second state. A low voltage (LV) transistor is coupled to the first current electrode of the HV transistor. An HV pad is coupled to the second current electrode of the HV transistor. An operating voltage rating of the HV pad exceeds an operating voltage rating of the LV transistor. A secondary electrostatic discharge protection device is coupled between the second current electrode of the HV transistor and a voltage supply terminal.

Abstract: A communication device determines a physical layer (PHY) transmission mode for transmitting a wakeup radio (WUR) packet. The communication device generates a first portion of the WUR packet, the first portion corresponding to a WLAN legacy PHY preamble and spanning a first frequency bandwidth. The communication device generates a second portion of the WUR packet, the second portion of the WUR packet spanning a second frequency bandwidth that is less than the first frequency bandwidth. The second portion of the WUR packet includes a PHY sync signal that corresponds to the selected PHY transmission mode, wherein the PHY sync signal is selected from a plurality of different PHY sync signals that respectively correspond to a plurality of different PHY transmission modes. The communication device generates a PHY data portion, within the second portion of the WUR packet, according to the selected transmission mode.

Abstract: A reverse current protection circuit for a switch circuit includes a reverse current control circuit and an enable/disable circuit coupled to the reverse current control circuit. The reverse current control circuit is coupled to an input terminal and an output terminal of the switch circuit, and disconnects the output terminal of the switch circuit from the input terminal of the switch circuit when an output voltage of the switch circuit is higher than a first predetermined voltage. The enable/disable circuit disables the reverse current control circuit for a first predetermined time period when the output voltage of the switch circuit becomes lower than the first predetermined voltage after being higher than the first predetermined voltage, and enables the reverse current control circuit after the first predetermined time period.

Abstract: A temperature compensated current controlled oscillator (CCO) including a first current generator configured to produce a proportional to absolute temperature (PTAT) current based upon a trim signal, a second current generator configured to produce a complementary to absolute temperature (CTAT) current based upon a temperature measurement, and a ring oscillator configured to receive the PTAT current and the CTAT current and to produce a frequency signal based upon the PTAT current and the CTAT current.

Abstract: A method includes using a first feedback loop to compensate for a first excess loop delay (ELD) associated with a first quantizer and a first DAC of the first feedback loop. The first quantizer provides a first quantizer output to a second feedback loop. A second feedback loop compensates for a second ELD associated a second quantizer and a second DAC of the second feedback loop. The second quantizer reduces a metastability error associated with the first quantizer output.