Abstract: A power converter including: a dual output resonant converter including a first output, a second output, a common mode control input, and a differential mode control input, wherein a voltage/current at the first output and a voltage/current at the second output are controlled in response to a common mode control signal received at the common mode control input and a differential mode control signal received at the differential mode control input; a dual output controller including a first error signal input, a second error signal input, a common mode control output, and a differential mode control output, wherein the dual output controller is configured to generate the common mode control signal and the differential mode control signal in response to a first error signal received at the first error signal input and a second error signal received at the second error signal input, wherein the first error signal is a function of the voltage/current at the first output and the second error signal is a function of

Abstract: A gain stage includes an offset cancellation loop coupled to a first amplifier. The first amplifier has a first transfer function and a first gain, and the offset cancellation loop includes a second amplifier having a second transfer function and a second gain. The second transfer function is based on an inverse of the first transfer function and the second gain based on an inverse of the first gain. When the offset cancellation loop feeds back an output signal of the first amplifier to an input of the first amplifier, a high-pass pole (or high-pass corner frequency) of the first amplifier is maintained at a constant level in spite of variations in the gain of the first amplifier. In one case, the second amplifier in the offset cancellation loop may be a simpler and lower power version of the first amplifier.

Abstract: A system for determining angular position includes a magnet having at least four poles and an axis of rotation, wherein the magnet produces a magnetic field. A first magnetic field sensor produces a first output signal and a second magnetic field sensor produces a second output signal in response to the magnetic field. The magnetic field sensors are operated in a saturation mode in which the magnetic field sensors are largely insensitive to the field strength of the magnetic field. Thus, the first output signal is indicative of a first direction of the magnetic field and the second output signal is indicative of a second direction of the magnetic field. Methodology performed by a processing circuit entails combining the first and second output signals to obtain a rotation angle value of the magnet in which angular error from a stray magnetic field is at least partially canceled.

Abstract: A communication system including an analog front end and an automatic gain controller. The analog front end includes at least one amplifier for amplifying a received analog signal and an analog to digital converter that converts the analog signal to digital samples. The automatic gain controller includes comparator circuitry, counter circuitry, and a gain controller. The comparator circuitry compares each of the digital samples with an upper threshold and a lower threshold. The counter circuitry counts a high count number of the digital samples having magnitudes that are greater than the upper threshold during each count window and counts a low count number of the digital samples having magnitudes that are less than the lower threshold during the count window. The gain controller adjusts a gain of the at least one amplifier by an amount based on the high count number and the low count number.

Abstract: One example discloses a combination near-field and far-field antenna configured to be coupled to a conductive host surface, including: a first feed point configured to be coupled to a far-field transceiver; a second feed point configured to be coupled to a near-field transceiver; a first conductive antenna surface; a first filter having a first interface coupled to both the first feed point and the first conductive antenna surface, and having a second interface coupled to the second feed point; wherein the first filter is configured to attenuate far-field signals passing between the first conductive antenna surface and the far-field transceiver from being received by the near-field transceiver; and wherein the first filter is configured to pass near-field signals between the near-field transceiver and the first conductive antenna surface.

Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain control stage, a filter stage, and an output stage. The gain control stage includes an input coupled at a first oscillator terminal configured and arranged for connection to a first terminal of a crystal. The filter stage includes an input coupled to an output of the gain control stage. The output stage includes a first transistor having a first current electrode coupled at a second oscillator terminal configured and arranged for connection to a second terminal of the crystal and a control electrode coupled to receive a voltage signal at the first oscillator terminal and a first bias voltage.

Abstract: Aspects are directed to an arrangement of circuits configured to generate and correct an output signal relative to a reference signal in response to a direction indication signal. Included in the arrangement of circuits is a phase-frequency detection circuit having logic circuitry configured to respond to the reference signal and a feedback signal by generating and updating the direction indication signal as a function of the logic states of an internal clock signal having risen and fallen. In this context, the feedback signal is generated by a feedback circuit in response to the output signal.

Abstract: A capacitive sensing circuit includes circuitry to compensate for moisture or liquid spanning sensor units. The capacitive sensing circuit includes input terminals that couple with respective sensor units to receive sensing signals. A sensing block determines capacitance changes in the sensor units using the sensing signals and generates output signals indicative of the sensed capacitance changes. First switches are coupled with respective ones of the input terminals and are closed during a first scanning stage to couple the sensing signals from the input terminals collectively to the sensing block. Second switches are coupled with respective ones of the input terminals and are closed during a second scanning stage, to generate compensation signals to compensate for capacitance interference between the sensor units.

Abstract: Systems and related methods are disclosed to manage memory for an integrated circuit including a processor and logic circuitry to manage the memory. The memory includes segments available for storage of data, and the processor stores data within the memory. Logic circuitry is configured to manage the memory, forms a plurality of sections within the segments, and applies tokens to the plurality of sections. Further, for each storage operation, the logic circuitry searches the tokens to identify blocks of continuous available tokens based upon data length, selects a block from the blocks identified in the search, determines a first token for the selected block, and outputs a memory address to the processor based upon the first token. The processor stores the data at the memory address. For one embodiment, the storage operations are associated with storage of data within packets received from network communications.

Abstract: A self-test apparatus for use in an electronic system includes an inter-chip communication bus, a plurality of circuit devices, circuitry including memory, and test controller circuitry. The plurality of circuit devices each has a distributed self-test controller circuit and analog, mixed signal or digital circuit elements. The distributed self-test controller circuits are integrated communicatively via the inter-chip communication bus and negotiate a self-test protocol with each other. The circuitry including memory stores self-test properties of the circuit elements, the self-test properties corresponding to an identifier of each of the circuit elements and a manner or protocol in which the circuit elements are tested. The test controller circuitry collects the self-test properties of the circuit elements and controls execution of the self-test according to the negotiated self-test protocol and the self-test properties.

Abstract: A radar device (100) is described that includes at least one transceiver (205) configured to support frequency modulated continuous wave (FMCW); a digital controller (262); and a temperature sensor system comprising a plurality of temperature sensors (222, 232, 242) coupled to various circuits (220, 230, 240) in the at least one transceiver (205). The digital controller (262) of the radar device (100) is configured to monitor a temperature of the various circuits (220, 230, 240) by polling temperature values of the plurality of temperature sensors (222, 232, 242).

Abstract: A transmitter circuit includes first and second carrier signal generators for generating corresponding first and second digital carrier signals, each having the same frequency. Modulation circuitry determines a phase shift value based on a received modulation signal. Outphasing circuitry generates a first digital output signal by adding the phase shift value to the phase of the first digital carrier signal and generates a second digital output signal by subtracting the phase shift value from the phase of the second digital carrier signal. A first switched-capacitor digital-to-analog converter (DAC) receives the first digital output signal and generates a first analog antenna output signal. A second switched-capacitor DAC receives the second digital output signal and generates a second analog antenna output signal. The sampling phases of the first and second DACs are opposite one another, whereby the first and second analog antenna output signals form a time-interleaved antenna output signal.

Abstract: A base station is configured to provides a beam change feedback channel for a user equipment to communicate unsolicited beam change feedback to the base station. If the user equipment determines that a beam other than the beam to which the user equipment is tuned has a stronger signal, the user equipment initiates a transmission on the beam change feedback channel to the base station indicating a beam change. The base station uses the feedback from the user equipment to update the beam to the user equipment.

Abstract: Embodiments detect the presence of proximity integrated circuit cards (PICCs) during wireless charging by analyzing the signal strength of a subcarrier within a near field communication (NFC) field. An NFC reader sends requests or other commands to stimulate a response from a PICC that may be in the operating area, and the presence of a PICC is determined based upon the signal strength for the subcarrier. For one embodiment, the subcarrier signal strength is compared to background values measured without stimulus to determine if a PICC is present in the operating area. As such, the presence of a PICC is detectable even where NFC communication with a PICC is unsuccessful because the PICC response is corrupted or not detectable due to interference. Once the presence of a PICC is determined, one or more actions can be taken to protect the PICC from damage due to wireless charging.

Abstract: A demodulator and method includes a plurality of correlation circuits, a result combining stage, and a time combining stage. The plurality of correlation circuits may be configured to output a plurality of correlation values that indicate a likelihood of whether a pattern of a buffered portion of an input data signal matches a first plurality of target frequency behavior patterns. The plurality of correlation circuits may be further configured to output a plurality of delayed correlation values that indicate a likelihood of whether a pattern of a delayed buffered portion of the input data signal matches a second plurality of target frequency behavior patterns, where both the buffered portion and the delayed buffered portion include a current symbol.

Abstract: A method for detecting zero-current of a voltage converter includes resetting a comparator output during a first period when a power switch of the voltage converter is turned on, and receiving, by an offset cancellation circuit, sample signals from the comparator. The method also determines a comparator offset using the sample signals. In response to an output voltage of the voltage converter being less than a threshold voltage, the comparator output is reset during a second period when the power switch is turned off. The comparator compares a first signal from the voltage converter with a second signal representing a ground voltage to generate a ZCD signal indicative of a comparison of the first and second signals. Then, an offset cancellation signal indicative of the determined comparator offset is generated to cancel the comparator offset.

Abstract: A phase to digital converter (PDC) generates a digital output that represents a phase difference between first and second clocks. The PDC includes a gated ring oscillator (GRO), which includes N signal delay elements coupled together in a ring via a logic gate, wherein a 1st signal delay element of the ring comprises an input coupled to an output of the logic gate, and wherein a Nth signal delay element of the ring comprises an output coupled to a first input of the logic gate. A convertor is coupled to the GRO and configured to generate low order bits of the digital output based on outputs of the logic gate and the N signal delay elements. A first counter includes an input coupled to an output of one of the N signal delay elements or the logic gate, wherein the first counter is configured to generate a first digital counter value.

Abstract: Aspects of the subject disclosure may include, for example, a method in which a selection is made for a first major constituent, a second major constituent and a minor constituent for forming a desired material. The method can include mixing the first major constituent, the second major constituent and the minor constituent in a single mixing step to provide a mixture of constituents. The method can include drying the mixture of constituents to provide a dried mixture of constituents and calcining the dried mixture of constituents to provide a calcinated mixture of constituents. The method can include processing the calcinated mixture of constituents (by a process including vacuum annealing and hot-pressing) to provide a sputtering target. Other embodiments are disclosed.

Abstract: A method and system are provided for supplying power with an LDO linear voltage regulator (110) having an LDO power supply (114, 115) and a load switch (116) by connecting a power supply voltage (102, 104) to a main core (121) and a standby core (122) in a multi-core low power microcontroller (120) during an active mode so that the standby core receives a first supply voltage that tracks the power supply voltage during the active mode, and upon detecting a standby mode for the multi-core low power microcontroller, disconnecting the power supply voltage from the standby core and connecting a low dropout (LDO) linear power supply voltage to the standby core during the standby mode so that the standby core receives the LDO linear power supply voltage as a second supply voltage during the standby mode.

Abstract: A multi-stage charge pump circuit including a first stage of the multi-stage charge pump having a first voltage output, a last stage of the multi-stage charge pump having a first voltage input, and an inter-stage limitation circuit configured to protect a voltage drop of the first voltage output of the first stage of the multi-stage charge pump when there is a voltage drop on the first voltage input of the last stage of the multi-stage charge pump.