Patents Assigned to NXP
  • Patent number: 10784821
    Abstract: The embodiments described herein provide radio frequency (RF) amplifiers, and in some embodiments provide amplifiers that can be used in high power RF applications. Specifically, the amplifiers described herein may be implemented with multiple resonant circuits to provide class F and inverse class F amplifiers and methods of operation. In general, the resonant circuits are implemented inside a device package with a transistor die to provide high efficiency amplification for a variety of applications.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: September 22, 2020
    Assignee: NXP USA, Inc.
    Inventors: Ning Zhu, Jeffrey Spencer Roberts, Damon G. Holmes
  • Patent number: 10784824
    Abstract: Apparatus are provided for amplifier systems and related circuits are provided. An exemplary circuit includes a main amplifier arrangement, first impedance matching circuitry coupled between the output of the main amplifier arrangement and a first circuit output, a peaking amplifier arrangement, and second impedance matching circuitry coupled between the output of the peaking amplifier arrangement and a second output of the circuit. In one exemplary embodiment, the first impedance matching circuitry and the second impedance matching circuitry have different circuit topologies and different physical topologies.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 22, 2020
    Assignee: NXP USA, Inc.
    Inventors: Basim H. Noori, Gerard J. Bouisse, Jeffrey K. Jones, Jean-Christophe Nanan, Jaime A. Pla
  • Patent number: 10784862
    Abstract: Embodiments described herein include radio frequency (RF) switches. In general, the embodiments described herein selectively bias the output terminals of one or more switching transistors in the RF switch. Such coupling can provide a bias that significantly reduces the effects of gate-lag. In one embodiment, the RF switch includes an antenna node, a first input/output (I/O) node, a second I/O node, a field-effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the output terminal(s).
    Type: Grant
    Filed: September 10, 2019
    Date of Patent: September 22, 2020
    Assignee: NXP USA, Inc.
    Inventors: Venkata Naga Koushik Malladi, Joseph Staudinger
  • Patent number: 10778233
    Abstract: A method for Phase Locked Loop (PLL) lock detection includes determining a phase error by comparing a feedback phase to a reference phase. A frequency error is determined by comparing a feedback frequency to a reference frequency. A lock signal is determined in response to the phase error being less than an upper phase threshold and greater than a lower phase threshold, and the frequency error being less than an upper frequency threshold and greater than a lower frequency threshold.
    Type: Grant
    Filed: August 14, 2019
    Date of Patent: September 15, 2020
    Assignee: NXP B.V.
    Inventor: Ulrich Moehlmann
  • Patent number: 10777899
    Abstract: A transmission line coupling arrangement comprising: a substrate comprising: a plurality of transmission lines each having a terminal radiating end for providing an electromagnetic wave as a result of a signal provided to the transmission line; and a footprint region extending over a portion of the substrate, wherein each of the terminal radiating ends of each of the plurality of transmission lines extend to a respective point within the footprint region; and the footprint region configured to receive a single transition housing thereover, the transition housing having at least one waveguide for receipt of the electromagnetic wave from one of the terminal radiating ends for coupling the at least one of the plurality of transmission lines to one of an output waveguide and an output antenna.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: September 15, 2020
    Assignee: NXP USA, INC.
    Inventors: Ziqiang Tong, Ernst Seler, Shamsuddin Ahmed
  • Patent number: 10771174
    Abstract: A digital broadcast receiver and method are provided. The digital broadcast receiver comprises an input, an anti-virus unit and a host interface. The input is configured to receive a digital broadcast. The anti-virus unit is configured to carry out an anti-virus check on the at least one data channel received as part of the digital broadcast. The host interface is configured to provide the at least one decoded data channel to a host.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventor: Henning Moeller
  • Patent number: 10769310
    Abstract: A method for protecting a machine learning model from copying is provided. The method includes providing a neural network architecture having an input layer, a plurality of hidden layers, and an output layer. Each of the plurality of hidden layers has a plurality of nodes. A neural network application is provided to run on the neural network architecture. First and second types of activation functions are provided. Activation functions including a combination of the first and second types of activation functions are provided to the plurality of nodes of the plurality of hidden layers. The neural network application is trained with a training set to generate a machine learning model. Using the combination of first and second types of activation functions makes it more difficult for an attacker to copy the machine learning model. Also, the neural network application may be implemented in hardware to prevent easy illegitimate upgrading of the neural network application.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Wilhelmus Petrus Adrianus Johannus Michiels, Gerardus Antonius Franciscus Derks
  • Patent number: 10771288
    Abstract: A processing module for a receiver device. The processor module comprises a channel estimate generation component arranged to output channel estimate information for a received signal, and a timestamping module arranged to determine a ToA measurement for a marker within a packet of the received signal based at least partly on the channel estimate information for the received signal generated by the channel estimate generation component. The channel estimate generation component comprises a validation component arranged to derive a validation pattern for the packet within the received signal for which a ToA measurement is to be determined, identify a section of the packet containing a validation sequence, and perform cross-correlation between at least a part of the validation sequence within the packet and at least a part of the generated validation pattern to generate channel estimate validation information.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Thomas Baier, Wolfgang Küchler, Frank Leong
  • Patent number: 10768228
    Abstract: Aspects of the present disclosure are directed to assessing integrity of communications circuitry. As may be implemented in accordance with one or more embodiments, a circuit node carries out a test protocol utilizing characteristics of a communication protocol to detect potential integrity issues. An initial test bit sequence is transmitted to circuit nodes connected to signal lines of a bus, by providing a test voltage across the signal lines that is less than an operating voltage potential of the bus. An ensuing state of the bus is sensed, and integrity of the bus or of circuitry connected to the bus is assessed based on the sensed state of the bus and on a state that the bus is expected to be in after transmission of the initial test bit sequence, which is used as an indication of whether all of the circuit nodes received the initial test bit sequence.
    Type: Grant
    Filed: April 5, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventor: Bernd Uwe Gerhard Elend
  • Patent number: 10771036
    Abstract: A system and method for tuning an impedance network of a device is provided. An RF signal is provided through a transmission path connected to an impedance matching network that includes a first variable component and a second variable component. A phase angle between a forward signal and a reflected signal along the transmission path is determined. Based on the phase angle between the forward signal and the reflected signal, the first variable component is modified to improve an impedance match between the RF signal source and the electrode. After modifying the first variable component, a ratio of a power of the reflected signal to a power of the forward signal is determined, and an inductance of the second variable component is modified to reduce the ratio of a power of the reflected signal to a power of the forward signal.
    Type: Grant
    Filed: November 17, 2017
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lionel Mongin, Pierre Marie Jean Piel, James Eric Scott
  • Patent number: 10769335
    Abstract: An electronic design automation (EDA) tool for executing topological and functional checks on an electronic circuit design (ECD) includes a processor and a memory that stores the ECD, graphical rules, and filter rules for executing the checks. The processor generates a test graph based on the ECD, replaces stretchable nodes with nested networks in the test graph to generate extended graphs, and decouples real edges and functional edges of each extended graph to generate real graphs and functional graphs, respectively. Based on the graphical rules, the processor executes the topological checks on an input graph of the ECD to identify real sub-graphs from the input graph that are isomorphic to a real graph. The processor further generates functional sub-graphs by combining a functional graph with each real sub-graph, and based on the filter rules, further executes the functional checks on the functional sub-graphs to identify output graphs.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Pushkar Sareen, Abinash, Piyush Pandey
  • Patent number: 10768280
    Abstract: The disclosure relates to a range-classifying-module for a radio receiver, the range-classifying-module configured to: receive a signal representative of a chirp from a transmitter, determine the presence of one or more pulses in the received signal; and classify the receiver as either proximal to or distal from the transmitter based on: one or more characteristics of the one or more pulses; in addition to a time-of-arrival of the one or more pulses.
    Type: Grant
    Filed: June 8, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Wolfgang Eber, Bernhard Spiess, Filippo Casamassima
  • Patent number: 10768290
    Abstract: A frequency estimation signal generator component arranged to receive an input frequency signal and to generate therefrom a frequency estimation signal. The frequency estimation signal generator component comprises a counter component arranged to sequentially output a sequence of control signal patterns over a plurality of digital control signals under the control of an oscillating signal derived from the received input frequency signal terns. The frequency estimation signal generator further comprises a continuous waveform generator component arranged to receive the plurality of digital control signals and a weighted analogue signal for each of the received digital control signals, and to output a continuous waveform signal comprising a sum of the weighted analogue signals for which the corresponding digital control signals comprise an asserted logical state.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Yu Lin, Erwin Janssen, Konstantinos Doris, Vladislav Dyachenko, Athon Zanikopoulos
  • Patent number: 10770539
    Abstract: An integrated circuit having a fingered capacitor with multiple metal fingers formed in inverted-trapezoid-shaped trenches in a multi-layer structure having a polish stop layer over an ultra-low-K dielectric layer over a low-K dielectric layer over a dielectric cap layer. The ultra-low-K dielectric layer reduces capacitance variations between the fingers, while the polish stop layer prevents metal height variations that would otherwise result from performing CMP directly on the ultra-low-K dielectric layer. The layered structure may include another low-K dielectric layer over the polish stop layer that provides a soft landing for the CMP. The polish stop layer may be removed after the CMP polishing and another ultra-low-K dielectric layer may be formed to encapsulate the tops of the metal fingers in the ultra-low-K dielectric material.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Chunshan Yin, Cheong Min Hong, Yu Chen
  • Patent number: 10766458
    Abstract: An electronic key a vehicle is disclosed. The electronic key includes an inertial sensor, a microcontroller coupled to the inertial sensor and a transmitter/receiver coupled to the microcontroller. The microcontroller is configured to perform an operation, the operation includes detecting a motion, turning a radio of the transmitter/receiver on, determining that a distance to the vehicle is less than a preselected distance, determining an activity using a sensor fusion process, determining that the distance to the vehicle is decreasing and performing a preselected operation on the vehicle.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Filippo Casamassima, Wolfgang Eber
  • Patent number: 10770540
    Abstract: A coplanar capacitor that incorporates teachings of the subject disclosure may include: a substrate; a voltage-tunable dielectric layer over the substrate; a plurality of bias lines over the voltage-tunable dielectric layer (wherein the bias lines are covered by an inter-level dielectric); a plurality of sidewall spacers (wherein each of the sidewall spacers is located adjacent one of the bias lines and each of the sidewall spacers spans between a respective portion of the voltage-tunable dielectric layer and a respective portion of the inter-level dielectric); and an electrode over the inter-level dielectric, and over portions of the voltage-tunable dielectric layer that are not covered by the plurality of bias lines and that are not covered by the sidewall spacers, wherein a plurality of gaps are disposed in the electrode. Other embodiments are disclosed.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Andrew Vladimir Claude Cervin, Marina Zelner
  • Patent number: 10768276
    Abstract: There is provided a radar sensor and method. The radar sensor comprises a plurality of transmit and receive antennas, a transceiver, a digital signal processor, a filter and an interface. The transceiver is configured to digitize received radar signals to provide a plurality of digital samples. The digital signal processor is configured to form a measurement matrix by transforming the plurality of digital samples into a distance/relative velocity matrix for each combination of the transmit and receive antennas. The filter is configured to identify samples forming the measurement matrix having a signal to noise ratio higher than a threshold value. The interface is configured to transmit the identified samples and their location in the measurement matrix to a remote host processor configured to further carry out direction of arrival processing on the identified samples.
    Type: Grant
    Filed: September 18, 2017
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventor: Feike Guus Jansen
  • Patent number: 10770457
    Abstract: Embodiments are provided for a capacitive array including: a first row of alternating first fingers and second fingers formed in a first conductive layer, wherein each first and second finger has a uniform width in a first direction and a uniform length in a second direction perpendicular to the first direction, the first row of alternating first and second fingers include a same integer number of first fingers and second fingers, and the first and second fingers are interdigitated in the first direction; and a first compensation finger formed in the first conductive layer at an end of the first row of alternating first and second fingers nearest a first outer boundary of the capacitive array, the first compensation finger configured to have an opposite polarity as a neighboring finger on the end of the first row.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Robert S. Jones, III, Xiankun Jin
  • Patent number: 10771019
    Abstract: A radio frequency (RF) power transistor circuit includes a power transistor and at least one decoupling circuit. The power transistor has a control electrode coupled to an input terminal for receiving an RF input signal, and a current electrode for providing an RF output signal at an output terminal. A decoupling circuit is coupled between the control electrode and a ground terminal, and/or between the current electrode and the ground terminal. The decoupling circuit includes a resistor coupled in series with components of a resonant circuit having a resonance that is lower than an RF frequency (e.g., lower than 20 megahertz). The resistor is for dampening the resonance of the resonant circuit.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: September 8, 2020
    Assignee: NXP USA, Inc.
    Inventors: Hussain H. Ladhani, Gerard J. Bouisse, Jeffrey K. Jones
  • Patent number: 10771266
    Abstract: In accordance with a first aspect of the present disclosure, a method for configuring a transponder is conceived, comprising: deriving a signature from a physical unclonable function; verifying said signature; initiating a key training sequence between a base station and the transponder in dependence on a result of verifying the signature. In accordance with other aspects of the present disclosure, a corresponding computer program, transponder and base station are provided.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: September 8, 2020
    Assignee: NXP B.V.
    Inventors: Juergen Nowottnick, Frank Graeber