Patents Assigned to NXP
  • Patent number: 10809277
    Abstract: A single axis inertial sensor includes a proof mass spaced apart from a surface of a substrate. The proof mass has first, second, third, and fourth sections. The third section diagonally opposes the first section relative to a center point of the proof mass and the fourth section diagonally opposes the second section relative to the center point. A first mass of the first and third sections is greater than a second mass of the second and fourth sections. A first lever structure is connected to the first and second sections, a second lever structure is connected to the second and third sections, a third lever structure is connected to the third and fourth sections, and a fourth lever structure is connected to the fourth and first sections. The lever structures enable translational motion of the proof mass in response to Z-axis linear acceleration forces imposed on the sensor.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: October 20, 2020
    Assignee: NXP USA, Inc.
    Inventors: Jun Tang, Andrew C. McNeil, Kajal Rahimian Kordestani
  • Patent number: 10811981
    Abstract: A power converter including: a dual output resonant converter including a first output, a second output, a common mode control input, and a differential mode control input, wherein a voltage/current at the first output and a voltage/current at the second output are controlled in response to a common mode control signal received at the common mode control input and a differential mode control signal received at the differential mode control input; and a dual output controller including a first error signal input, a second error signal input, a delta power signal input, a common mode control output, and a differential mode control output, wherein the dual output controller is configured to generate the common mode control signal and the differential mode control signal in response to a first error signal received at the first error signal input and a second error signal received at the second error signal input, wherein the first error signal is a function of the voltage/current at the first output and the seco
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventor: Hans Halberstadt
  • Patent number: 10812199
    Abstract: One example discloses a near-field wireless device, including: a near-field antenna; a variable current source; a controller coupled to the near-field antenna and the variable current source; wherein the controller is configured to measure a transmit quality-factor (Qtx) of the near-field antenna; and wherein the controller is configured to increase current sent by the variable current source to the near-field antenna if the measured Qtx is lower than a minimum Qtx.
    Type: Grant
    Filed: August 28, 2019
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventors: Anthony Kerselaers, Liesbeth Gommé
  • Patent number: 10811959
    Abstract: Embodiments of switched capacitor voltage converters and methods for operating a switched capacitor voltage converter are disclosed. In an embodiment, a switched capacitor voltage converter includes serially connected switching devices, a voltage generator connected to the serially connected switching devices and configured to generate driver voltages in response to a first voltage at a first terminal that is connected to the serially connected switching devices, and voltage drivers configured to drive the serially connected switching devices based on the driver voltages.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventor: Bin Shao
  • Patent number: 10812149
    Abstract: One example discloses a multi-mode near-field device configured to be coupled to a conductive host surface, including: a conductive antenna surface configured as a near-field electrically inductive (NFEI) antenna; wherein the conductive antenna surface includes a first region and a second region; wherein the first region is configured to be capacitively coupled to the conductive host surface; wherein the second region is configured to be galvanically or capacitively coupled to the conductive host surface; wherein the multi-mode device is configured to operate in, a first mode when the second region is galvanically coupled to the conductive host surface; and a second mode when the second region is capacitively coupled to the conductive host surface.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventors: Anthony Kerselaers, Liesbeth Gommé
  • Patent number: 10812119
    Abstract: Interference cancellation is provided, according to certain aspects, by a filter, a signal detection circuit, synthesis circuitry and signal-generation circuitry. The filter is used to filter an incoming signal having an associated signal-to-noise metric and to output therefrom a filtered signal having an interference attribute of the incoming signal by amplification and/or isolation. The signal detection circuit is used to detect the interference attribute in the filtered signal. The synthesis circuitry is used to synthesize interference in the incoming signal based on the interference attribute. The signal-generation circuitry is used to generate, in response to the synthesized interference in the incoming signal, a filtered version of the incoming signal which provides an improved signal-to-noise metric.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventors: Massimo Ciacci, Arie Geert Cornelis Koppelaar, Alessio Filippi, Lucien Johannes Breems
  • Patent number: 10812067
    Abstract: Embodiments of redrivers and resistive units for redrivers are disclosed. In an embodiment, a resistive unit for a redriver includes at least one resistor connected to an input/output terminal of the redriver, at least one switch serially connected to the at least one resistor, and a voltage regulator connected to the at least one switch and configured to generate a termination voltage for the at least one switch. Instead of grounding the at least one resistor, using the voltage regulator can avoid large voltage jump at input/output terminals to keep connected devices safe.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventors: Siamak Delshadpour, Xu Zhang
  • Patent number: 10812126
    Abstract: One example discloses a near-field device, including: an electric (E-Field) antenna including a first conductive plate and a second conductive plate responsive to non-propagating quasi-static electric near-field signals; wherein the electric antenna is configured to be coupled to a transceiver circuit; a substrate configured to be worn by a user; wherein the first conductive plate is located on a first side of the substrate configured to face away from the user; and wherein the second conductive plate is located on a second side of the substrate configured to face toward the user.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: October 20, 2020
    Assignee: NXP B.V.
    Inventors: Anthony Kerselaers, Liesbeth Gommé
  • Patent number: 10811502
    Abstract: A method for manufacturing a super-junction MOSFET entails forming a recessed shield electrode in a trench in a semiconductor layer of a substrate, the trench being lined with a first oxide layer. When the electrically conductive material forming the shield electrode is removed to recess the shield electrode, the first oxide layer on sidewalls of the trench is exposed. Removal of the first oxide layer from the sidewalls and from shield sidewalls of the electrode produces openings at a top part of the shield sidewalls. A second oxide layer is formed over the shield electrode and fills the openings. Part of the second oxide layer is removed to expose a top surface of the shield electrode. A gate dielectric is formed over the top surface of the shield electrode and conductive material is deposited over the gate dielectric in the trench to form a gate electrode of the MOSFET.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: October 20, 2020
    Assignee: NXP USA, Inc.
    Inventors: Vishnu Khemka, Tanuj Saxena, Ganming Qin, Raghuveer Vankayala Gupta, Mark Edward Gibson, Moaniss Zitouni
  • Patent number: 10812080
    Abstract: A method for high-speed voltage level translation includes biasing a high-voltage (HV) gate of an HV transistor to an intermediate voltage with a bias device. A low-voltage (LV) transistor is activated with a positive voltage transition applied to an LV gate of the LV transistor, wherein the HV transistor is connected in series between an output and an LV drain of the LV transistor. The intermediate voltage is bootstrapped to a bootstrapped voltage in response to the positive voltage transition on the LV gate coupled to the HV gate through a capacitor therebetween. The output is discharged. A time constant, defined by a resistance of the bias device and a capacitance of the capacitor, is greater than a minimum time constant, thereby maintaining the bootstrapped voltage on the HV gate at or above a drive voltage for a minimum period to discharge the output to a minimum voltage.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: October 20, 2020
    Assignee: NXP USA, Inc.
    Inventors: John Pigott, Trevor Mark Newlin
  • Patent number: 10802521
    Abstract: A voltage regulation system has a voltage regulator, a current-limiting circuit, and a feed-forward circuit. The voltage regulator regulates an output voltage to a desired voltage level. The current-limiting circuit controls an output current of the voltage regulator to a desired current level. The feed-forward circuit, which has a fast response time, controls an inrush current in the output current caused by a decrease in an output voltage.
    Type: Grant
    Filed: January 1, 2019
    Date of Patent: October 13, 2020
    Assignee: NXP USA, Inc.
    Inventors: Liang Qiu, Meng Wang, John Pigott
  • Patent number: 10804957
    Abstract: A preamble detection system and method includes converting the phase domain input samples corresponding to the preamble into frequency domain input samples. An I/Q-formatted dot product is generated from a dot product process between the frequency domain input samples and a reference pattern indicative of an expected preamble. The I/Q-formatted dot product is averaged with at least one previously generated I/Q-formatted dot product to generate an I/Q-formatted averaged dot product. The I/Q-formatted averaged dot product is converted into a polar-formatted averaged dot product, wherein the polar-formatted averaged dot product includes a magnitude of the polar-formatted averaged dot product and an angle of the polar-formatted averaged dot product. A preamble-found signal is then generated in response to the magnitude of the polar-formatted averaged dot product exceeding a preamble magnitude threshold.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: October 13, 2020
    Assignee: NXP USA, Inc.
    Inventors: Claudio Gustavo Rey, Raja Venkatesh Tamma
  • Patent number: 10806021
    Abstract: A packaged microelectronic component includes a substrate and a semiconductor die coupled to a top surface of the substrate. A method of attaching the packaged microelectronic component to a secondary structure entails applying a metal particle-containing material to at least one of a bottom surface of the substrate and a mounting surface of the secondary structure. The packaged microelectronic component and the secondary structure are arranged in a stacked relationship with the metal particle-containing material disposed between the bottom surface and the mounting surface. A low temperature sintering process is performed at a maximum process temperature less than a melt point of the metal particles to transform the metal particle-containing material into a sintered bond layer joining the packaged microelectronic component and the secondary structure. In an embodiment, the substrate may be a heat sink for the packaged microelectronic component and the secondary structure may be a printed circuit board.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: October 13, 2020
    Assignee: NXP USA, Inc.
    Inventors: Lakshminarayan Viswanathan, Lu Li, Mahesh K. Shah, Paul Richard Hart
  • Patent number: 10805892
    Abstract: A method for communication includes respectively associating each of a plurality of client stations (STAs) with at least one basic service set (BSS) of at least one access point (AP) in a WLAN. The APs in the WLAN are synchronized prior to transmitting data to the STAs. First and second groups of the antennas are defined for downlink communication with the first and second STAs, each of the groups including antennas belonging to at least two of the APs. Different, first and second distributed beamforming parameters are computed over the first and second groups of the antennas. Respective data for transmission to the first and second STAs are distributed to the APs to which the antennas in the respective first and second groups belong and are transmitted in synchronization in accordance with the first and second distributed beamforming parameters.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 13, 2020
    Assignee: NXP USA, Inc.
    Inventors: B Hari Ram, Sri Varsha Rottela, Vijay Ahirwar, Sudhir Srinivasa, Nilesh N Khude
  • Patent number: 10802932
    Abstract: A data processing system and methods for operating the same are disclosed. The method includes detecting a fault by comparing output signals from a first processing core and a second processing core, entering a safe mode based upon detecting the fault, completing transactions while in the safe mode, and determining whether the fault corresponds to a hard error. Based upon the fault corresponding to a hard error, one of processing cores is identified as a faulty core. The faulty core is inhibited from executing instructions and the other processing core is allowed to execute instructions.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: October 13, 2020
    Assignee: NXP USA, Inc.
    Inventors: Jehoda Refaeli, Nancy Hing-Che Amedeo, Larry Alan Woodrum
  • Patent number: 10804945
    Abstract: The present disclosure describes apparatuses and methods for dynamic interference cancellation in wireless receivers. In some aspects, a signal vector transmitted through a wireless environment is received via multiple antennas of a receiver, the signal vector affected by interfering signals in the wireless environment. The receiver determines an interference channel matrix for the signal vector based on the interference received with the signal vector and selects, from the interference channel matrix, columns of the interference channel matrix to form a noise-cancelling equalization matrix. The receiver then equalizes the signal vector with the noise-cancelling equalization matrix to remove a portion of interference from the signal vector to provide noise-cancelled equalized values of the signal vector for decoding. By so doing, the receiver may reduce effects of interference of the wireless environment (e.g.
    Type: Grant
    Filed: October 31, 2018
    Date of Patent: October 13, 2020
    Assignee: NXP USA, Inc.
    Inventors: B Hari Ram, Lokesh Sundaramurthy Satrasala, Sudhir Srinivasa, Hongyuan Zhang
  • Patent number: 10805092
    Abstract: A processing module for a first lock device of a range determination system, the range determination system comprising a lock group comprising a plurality of lock devices of which the first lock device forms part, the plurality of lock devices physically spaced over a lockable element and configured to communicate with a key group comprising a plurality of key devices, a shortest distance between any one of the key devices of the key group and any one of the lock devices of the lock group providing for access to the lockable element relative to a threshold distance.
    Type: Grant
    Filed: February 19, 2018
    Date of Patent: October 13, 2020
    Assignee: NXP B.V.
    Inventors: Jan Dutz, Wolfgang Küchler, Frank Leong, Thomas Baier, Arie Geert Cornelis Koppelaar
  • Publication number: 20200319884
    Abstract: A system, method, apparatus and integrated circuit are provided for collecting runtime performance data with a set of hardware timers under control of a dedicated hardware control register by connecting a central processing unit (CPU) and memory to a timer block bank having a plurality of timer instances which are selectively enabled and activated to collect runtime performance data during execution of application code by measuring specified software execution events, where the dedicated hardware control register includes a plurality of register fields for independently controlling activation behavior of the plurality of timer instances in response to a single write operation to all register fields in the hardware control register.
    Type: Application
    Filed: June 4, 2019
    Publication date: October 8, 2020
    Applicant: NXP USA, Inc.
    Inventors: Michael Rohleder, George A. Ciusleanu, Frank Steinert
  • Patent number: 10797891
    Abstract: A physically unclonable function (PUF) system is provided. The PUF system includes an entropy source, a plurality of selectable paths, a random selection block, and error correction logic. The plurality of selectable paths are formed between the entropy source and an output for providing a PUF response. The random selection block is for randomly selecting one of the plurality of selectable paths in response to receiving a challenge. The error correction logic is coupled to the output for receiving the PUF response and for correcting any errors in the PUF response for the plurality of selectable paths. By using a different path through the entropy source each time a challenge is received, protection is provided against side-channel attacks.
    Type: Grant
    Filed: April 17, 2018
    Date of Patent: October 6, 2020
    Assignee: NXP B.V.
    Inventor: Xiaoxu Yao
  • Patent number: 10794701
    Abstract: An inertial sensor includes a movable element having a mass that is asymmetric relative to a rotational axis and anchors attached to the substrate. First and second spring systems are spaced apart from the surface of the substrate. Each of the first and second spring systems includes a pair of beams, a center flexure interposed between the beams, and a pair of end flexures. One of the end flexures is interconnected between one of the beams and one of the anchors and the other end flexure is interconnected between one of the beams and the movable element. The beams are resistant to deformation relative to the center flexure and the end flexures. The first and second spring systems facilitate rotational motion of the movable element about the rotational axis and the spring systems facilitate translational motion of the movable element substantially parallel to the surface of the substrate.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: October 6, 2020
    Assignee: NXP USA, Inc.
    Inventor: Andrew C. McNeil