Abstract: In accordance with a first aspect of the present disclosure, a method of designing an integrated circuit is conceived, comprising: placing integrated circuit cells that include supply pins in a plurality of predefined rows; determining blocked areas for supply pin extensions; extending the supply pins outside said blocked areas. A corresponding integrated circuit is also provided.

Abstract: There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state.

Abstract: Disclosed herein is a conductive structure that serves as both a control terminal and a field plate for a transistor. The transistor includes a channel region including a portion located in a vertical sidewall of semiconductor material that separates an upper level portion and a lower level portion of the semiconductor material. An extended drain region includes a portion located in the lower portion of the semiconductor material. The conductive structure is laterally adjacent to the vertical sidewall and includes a first vertical side and an opposite second vertical side with the first vertical side being closer to the vertical component sidewall. The first side is vertically closer to the lower level portion of the semiconductor material than the second vertical side.

Abstract: One example discloses a segmented platform, including: a set of cells configured to receive a set of different items; a cell content circuit configured to map each different item to at least one of the cells; a set of visual indicators coupled to the set of cells; and a cell selector circuit configured to identify a selected item from the set of different items and activate a visual indicator from the set of visual indicators corresponding to a selected cell from the set of cells that is configured to contain the selected item.

Abstract: A transistor device includes a channel region including a portion located in a vertical sidewall of semiconductor material and an extended drain region including a portion located in a lower portion of the semiconductor material. In one embodiment, a control terminal of the transistor device is formed by forming a conductive sidewall spacer structure adjacent to the sidewall and a field plate for the transistor device is formed by forming a second conductive sidewall spacer structure.

Abstract: A programmable divider is provided. The programmable divider includes a clock input coupled to receive a clock signal, a control input coupled to receive a first control signal, a counter compare block, and a load block. The counter compare block is configured to receive a first load value, update a counter with the first load value, provide a first output signal, and when the first control signal is at a first value, generate a first pulse in the first output signal when the counter reaches an end value. The load block is configured to receive a first divider value and provide the first load value based on a current counter value of the counter.

Abstract: An apparatus configured to provide for detection and ranging of a remote object, the apparatus configured to perform the following: based on a first reflected signal comprising a reflection from the remote object of a first frequency varying detection signal that varies in frequency over a first bandwidth; and based on a second reflected signal comprising a reflection from the remote object of a second frequency varying detection signal that varies in frequency over a different second bandwidth; determine a first estimated range based on a first beat frequency signal comprising the first reflected signal mixed with the first frequency varying detection signal; determine a second estimated range based on a second beat frequency signal comprising the second reflected signal mixed with the second frequency varying detection signal; determine a range of the remote object as a function of the first estimated range and the second estimated range.

Abstract: A matching circuit comprising: an input-terminal configured to be connected to an active-circuit; an output-terminal configured to be connected to a downstream component; a current-source configured to provide a disabled-current; one or more diode-modules, each comprising a diode and a biasing-resistor in parallel with each other; and a reactive-matching-component that has a reactive impedance. The current source is configured to pass the disabled-current through the one or more diode-modules and the reactive-matching-component when the matching circuit is in a disabled-mode of operation such that they contribute to the impedance of the matching circuit between the input-terminal and the output-terminal.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate, a first dielectric layer disposed over a semiconductor substrate, a source electrode and a drain electrode formed over the semiconductor substrate within openings formed in the first dielectric layer, a gate electrode formed over the semiconductor substrate between the source electrode and the drain electrode, and a protection layer disposed on the source electrode, the drain electrode, and the first dielectric layer, wherein a first edge of the protection layer terminates the protection layer between the source electrode and the gate electrode, and a second edge of the protection layer terminates the protection layer between the gate electrode and the drain electrode. A method for fabricating the semiconductor devices includes forming a first dielectric layer over the semiconductor substrate, forming source and drain electrodes, depositing the protection layer over the source and drain electrodes, and forming the gate electrode.

Abstract: An apparatus and method for synchronously discharging multiple capacitive loads. In one embodiment, the apparatus includes first and second discharge circuits for discharging first and second capacitive loads, respectively. The apparatus also includes a control circuit coupled to the first and second discharge circuits and configured to control the second discharge circuit. The control circuit includes a first scaler circuit configured to generate a first scaled voltage based on a first voltage on the first capacitive load, a second scaler circuit configured to generate a second scaled voltage based on a second voltage on the second capacitive load, and a comparator circuit for comparing the first and second scaled voltages. The comparator circuit asserts a control signal when the second scaled voltage exceeds the first scaled voltage. The second discharge circuit discharges the second capacitive load when the comparator circuit asserts its control signal.

Abstract: Embodiments are provided for voltage regulators that include a first, a second, a third, and a fourth NMOS transistor cascoded between a high voltage source and a low voltage output; a resistor network including a first, a second, a third, and a fourth resistor connected in series between the high voltage source and ground, wherein gate electrodes of the second, third, and fourth NMOS are respectively connected to nodes between the first and second resistors, the second and third resistors, and the third and fourth resistors; and a multi-stage charge pump configured to provide a first bias voltage to a gate electrode of the first NMOS and a second bias voltage to the gate electrode of the second NMOS.

Abstract: Embodiments of RF amplifiers and RF amplifier devices include a transistor, a multiple-section bandpass filter circuit, and a harmonic termination circuit. The bandpass filter circuit includes a first connection node coupled to the amplifier input, a first inductive element coupled between the first connection node and a ground reference node, a first capacitance coupled between the first connection node and a second connection node, a second capacitance coupled between the second connection node and the ground reference node, and a second inductive element coupled between the second connection node and the transistor input. The harmonic termination circuit includes a third inductive element and a third capacitance connected in series between the transistor input and the ground reference node. The harmonic termination circuit resonates at a harmonic frequency of a fundamental frequency of operation of the RF amplifier.

Abstract: In generating a physical layer (PHY) data unit for transmission via a communication channel, information bits to be included in the PHY data unit are received. A number of padding bits are added to the information bits. The number of padding bits is determined based on respective virtual values of each of one or more encoding parameters. The information bits are parsed to a number of encoders and are encoded, using the number of encoders, to generate coded bits. The coded bits are padded such that padded coded bits correspond to respective true values of each of the one or more encoding parameters. The PHY data unit is generated to include the padded coded bits.

Abstract: A receive path arrangement of a radar sensor of FMCW type comprising a first and second receive path configured to receive reflected radar signals for detection and ranging of objects in a space around the radar sensor; the first receive path configured to provide reflected radar signals between a first and second beat frequency to a first analogue to digital converter for subsequent digital signal processing and wherein; the second receive path includes a second-receive-path filter configured to provide filtered signals by attenuation of the reflected radar signals having frequencies below an intermediate beat frequency, the intermediate beat frequency between the first and second beat frequencies, the second receive path further including a second-receive-path amplifier arrangement configured to provide amplified signals by amplification of the filtered signals and provide the amplified signals to a second analogue to digital converter for subsequent digital signal processing.

Abstract: In a data processing system having a processor and a memory protection unit (MPU), a method includes scheduling, in the processor, a new process to be executed; writing a process identifier (PID) corresponding to the new process into storage circuitry of the MPU; in response to updating the storage circuitry with the PID, configuring the MPU with region descriptors corresponding to the new process; configuring, by an operating system of the processor, the processor to execute the new process in parallel with the configuring the MPU with the region descriptors; and when the configuring the MPU is complete, giving control to the new process to execute on the processor.

Abstract: Nested microstrip systems and methods, and systems and methods encompassing same, are disclosed herein. In one example, a nested microstrip system includes a printed circuit board (PCB) having first and second layer levels, where first and second conductive traces are positioned at the second layer level. The first conductive trace is configured to include an orifice, and to extend between first and second locations along a first path, and the second conductive trace is positioned within the orifice. A non-conductive gap portion of the orifice exists between the first and second conductive traces so that the second conductive trace is electrically isolated from the first conductive trace. One or more first electromagnetic signals can be propagated along a first part of the first conductive trace, and one or more second electromagnetic signals can be propagated along at least a second part of the second conductive trace.

Abstract: Power amplifiers, amplifier systems, and related methods are disclosed herein. In one example embodiment, the amplifier system includes a bias controller that enables fast switching between an on state bias voltage and an off state bias voltage for the power amplifier. The bias controller can transition a low impedance switch to an on state to electrically couple a first electrode of a charge holding capacitor to an input of the power amplifier. The charge holding capacitor can be pre charged with the on state bias voltage to quickly provide the on state bias voltage to the power amplifier. The bias controller can also transition the low impedance switch to an off state to couple the input of the power amplifier to the off state bias voltage.

Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.

Abstract: A method of wafer dicing includes singulating dies from a semiconductor wafer. The method further includes depositing a metal layer on back sides of the singulated dies, wherein a portion of the metal layer continues beyond the backs sides of the singulated dies to deposit at least partially on lateral sides of the singulated dies. A packaged die includes a semiconductor die and a metal outer layer deposited on the back side of the semiconductor die and on a portion of the lateral side of the semiconductor die nearest the back side. The packaged die further includes a substrate mounted to the back side of the semiconductor die a die attach material that bonds the substrate to the metal outer layer deposited on the semiconductor die, wherein the metal outer layer and the die attach material surround the back edge of the semiconductor die.

Abstract: Embodiments of An apparatus and method are disclosed. In an embodiment, an apparatus for performing digital infinite impulse response filtering includes a biquad core that includes five multiplier elements, each multiplier element including, a multiplier, a first delay element in series with and after the multiplier, and a second delay element in series with and after the first delay element, and a multiplexer associated with each of the five multiplier elements, each multiplexer configured to provide one of at least two different coefficients to the multiplier of the corresponding multiplier element.