Abstract: A controller for a DC-DC converter that includes an inductor. The DC-DC converter has three phases of operation: a first phase, in which an input voltage charges the inductor; a second phase, in which the inductor discharges to a load; and a third phase, in which the inductor is disconnected from the load and in which the input voltage does not charge the inductor. The controller is configured to set a control-factor based on the input voltage of the DC-DC converter, and set the duration of the third phase based on the control-factor and the sum of the duration of the first phase and the second phase.

Abstract: A double IO pad cell including a busing frame formed on a busing metal layer aligned with a same-sized component frame integrated on a component layer of an IC. The busing frame includes first and second IO pads, a supply voltage rail, and a ground voltage rail. The component frame includes first and second primary ESD circuitry each including a first diode coupled between a respective one of the first and second IO pads and the supply voltage rail and a second diode coupled between the respective IO pad and the ground voltage rail. The second diodes of each primary ESD circuitry are integrated adjacent each other sandwiched between the first diodes which act as collector guard bands for the second diodes. The diodes of each primary ESD circuitry of the component frame are aligned with a corresponding one of the first and second IO pads of the busing frame.

Abstract: A wireless network includes a client device and an access point (AP). The client device generates a data packet having a physical layer protocol data unit frame format. The client device transmits the data packet to the AP such that a plurality of long training fields (LTFs) of the data packet is transmitted at higher power as compared to a data field of the data packet, and a preamble portion of the data packet is transmitted at higher power as compared to the plurality of LTFs. Further, the data field includes various resource units (RUs) and one such RU is utilized for data transmission between the client device and the AP. The transmission of the data packet from the client device to the AP in the aforementioned manner results in the range extension of the wireless network.

Abstract: Embodiments of level shifters are disclosed. In an embodiment, a level shifter includes a transistor connected between an input terminal of the level shifter and an output terminal of the level shifter, a first resistor connected between a first terminal of the transistor and one of the input terminal of the level shifter and the output terminal of the level shifter, a capacitor connected between the input terminal of the level shifter and the output terminal of the level shifter, a current source connected between the output terminal of the level shifter and a fixed voltage, and a resistor divider connected between the first resistor and the output terminal of the level shifter.

Abstract: A self-calibrating digital-to-analog converter (DAC) is disclosed. The self-calibrating DAC includes a DAC including a least significant bit (LSB) side resistor network and a most significant bit (MSB) side resistor network. At least the MSB side resistor network includes a plurality of trimmable resistors. A resistance to frequency converter coupled with an output of the DAC is included to generate a frequency fL based on a value of the LSB side resistor network or the MSB side resistor network. A monitor is included to generate a counter value by comparing fL with a high frequency clock having a constant frequency fH.

Abstract: A method of forming a packaged semiconductor device includes attaching a backside surface of a semiconductor die to a major surface of a package substrate. A first conductive connector is formed over a portion of an active surface of the semiconductor die and a portion of the major surface of the package substrate. A first conductive connection between a first bond pad of the semiconductor die and a first substrate pad of the package substrate is formed by way of the first conductive connector. A bond wire connects a second bond pad of the semiconductor die to a second substrate pad of the package substrate. The first bond pad located between the second bond pad and an edge of the semiconductor die.

Abstract: A CAN module that can be integrated between a CAN controller and a CAN transceiver includes a receive data (RXD), input interface for receiving a first bit sequence through a RXD stream and a RXD output interface for sending a manipulated receive data (MRXD), stream including a second bit sequence. A processing logic of the CAN module is configured to manipulate the first bit sequence to generate a second bit sequence comprising a second stuff bit at a second position in the second bit sequence corresponding to a first position of a first stuff bit in the first bit sequence such that the second stuff bit is complementary to a preceding bit of the second stuff bit in the second bit sequence. The present disclosure also relates to a method for the CAN module.

Abstract: Various implementations relate to a data processing system comprising instructions embodied in a non-transitory computer readable medium, the instructions for a cryptographic operation including a masked decomposition of a polynomial a having ns arithmetic shares into a high part a1 and a low part a0 for lattice-based cryptography in a processor, the instructions, including: performing a rounded Euclidian division of the polynomial a by a base ? to compute t(?)A; extracting Boolean shares a1(?)B from n low bits of t by performing an arithmetic share to Boolean share (A2B) conversion on t(?)A and performing an AND with ??1, where ?=???1 is a power of 2; unmasking a1 by combining Boolean shares of a1(?)B; calculating arithmetic shares a0(?)A of the low part a0; and performing a cryptographic function using a1 and a0(?)A.

Abstract: Various embodiments relate to a system for provisioning a cryptographic device, including: a memory; a processor coupled to the memory, wherein the processor is further configured to: determine a maximum PQC private key size, maximum PQC public key size, and maximum PQC updater size of a plurality of post quantum cryptography algorithms; provision memory in the cryptographic device to store a PQC-update non-PQC private key, a secret PQC-update non-PQC public key, PQC private key, PQC public key, and PQC updater based upon the determined maximum PQC private key size, maximum PQC public key size, and maximum updater size; and provision the cryptographic device with the PQC-update non-PQC private key, the secret PQC-update non-PQC public key, a non-PQC secret key, a non-PQC public key, and non-PQC algorithm code configured to carry out non-PQC cryptographic algorithms.

Abstract: Electrostatic discharge protection circuitry includes a transistor pass-gate coupled between potential source of electrostatic discharge-driven current (“ESD current”) and an input node of a circuit block is configured provide a sufficiently resistive current path between a first current terminal and a second current terminal of the pass gate such that, when an amount of charge sufficient to cause an ESD event accumulates at the potential ESD current source, a sufficient voltage drop occurs across the pass gate such that devices coupled to the input node of the circuit block are protected from experiencing a voltage drop across them that is above a predetermined threshold voltage.

Abstract: Aspects of the disclosure are directed to an apparatus having a multi-link device (MLD) including processing circuitry to communicate signals with one of a plurality of remote devices over multiple communications link. The MLD and the one of the remote devices operate in first and second communication-specific configurations as follows. A physical layer convergence procedure protocol data unit (PPDU) is transmitted in one of the links while a PPDU is communicated in another one of the links under a first configuration. A PPDU is communicated in a first one of the respective communications links with an ending time set based on a PPDU communicated in a second one of the respective communications links in a second configuration. Such approaches may be carried out based on capabilities relating to simultaneous transmission and reception of MLDs that are communicating.

Abstract: A data processing system has a processor and a system memory. The system memory may be a dynamic random-access memory (DRAM). The processor includes an embedded memory. The system memory is coupled to the processor and is organized in a plurality of pages. A portion of the code or data stored in the plurality of memory pages is selected for permutation. A permutation order is generated and the memory pages containing the portion of code or data is permuted using a permutation order. The permutation order and/or a reverse permutation order to recover the original order may be stored in the embedded memory. Permuting the memory pages with a permutation order stored in the embedded memory prevents the code or data from being read during a freeze attack on the system memory in a way that is useful to an attacker.

Abstract: Field effect transistors in an electronic switching device are provided with electrostatic discharge (ESD) protection elements electrically coupled to a first current terminal of each transistor (e.g., a source of each transistor or a drain of each transistor), allowing the electronic switching device to withstand ESD-induced currents without damage to the switching device.

Abstract: It is described a method, a control device, and a computer program for enabling/disabling at least one near field communication (NFC) function of a mobile device (MD). It is further described such a MD. The method comprises (a) associating the at least one NFC function to be enabled/disabled with a corresponding secure application (SA) installed in a secure element (SE) system; (b) checking whether the SA complies with a predefined secure condition; (c) if the SA complies with the predefined secure condition, transmitting a notification from the SA to the NFC control system (NFCC) via an interface between the SE system and the NFCC; and (d) enabling/disabling, by the NFCC, the at least one NFC function based on information comprised by the transmitted notification.

Abstract: A method is provided for partitioning a plurality of devices in a communications system. The method includes providing the communications system with a central server that communicates with each of the plurality of devices. The communications system communicates in a plurality of time periods. The plurality of devices is partitioned into two or more groups of devices. Time periods of the plurality of time periods are assigned for communications of the two or more groups of devices. Time intervals between the time periods for the two or more groups are determined to be co-prime time intervals greater than one, and each of the two or more groups is assigned a different time interval of the co-prime time intervals. The two or more groups are active for communications only during the assigned time periods determined by the co-prime time intervals. A device is also provided for operating in the communications system.

Abstract: A radar processor for processing a frame of radar data received from one or more targets, the frame of radar data having a carrier frequency and comprising a sequence of codewords with a codeword repetition interval, wherein the carrier frequency and the codeword repetition interval define an unambiguous velocity range, the radar processor configured to: receive the frame of radar data; transform the frame to obtain a velocity data array; apply a correction algorithm to the velocity data array to correct a Doppler shift of the frame to obtain a corrected array, wherein the correction algorithm comprises a set of Doppler correction frequencies corresponding to a set of velocity gates and at least one of the set of Doppler correction frequencies corresponds to a velocity gate outside the unambiguous velocity range; and perform range processing on the corrected array to obtain a range-Doppler map.

Abstract: A device package includes a die that includes a substrate having first and second surfaces. A sensor is formed at a sensor region of the first surface. A trench extends entirely through the substrate between the first and second surfaces, in which the trench at least partially surrounds the sensor region. An isolation material, formed at the first surface, may extend across the trench A ring structure is coupled to the first surface of the substrate to create a first cavity in which the sensor is contained, the ring structure being laterally displaced away from and surrounding the sensor region and the trench. A molded compound body may abut an outer wall of the ring structure. The molded compound body has a second cavity that is concentric with the first cavity to enable fluid communication between the sensor and an environment external to the device package.

Abstract: A thermal interface structure for transferring heat from an electronic component to a system heat sink includes a stack of one or more layers of a stiff thermal interface material and one or more layers of a compliant thermal interface material stacked on and connected to the one or more layers of the compliant thermal interface material. In some embodiments, the thermal interface structure also may include one or more layers of a shape memory alloy and/or a collapsible encasement.

Abstract: A method is provided for watermarking a machine learning model used for object detection. In the method, a first subset of a labeled set of ML training samples is selected. Each of one or more objects in the first subset includes a class label. A pixel pattern is selected to use as a watermark in the first subset of images. The pixel pattern is made partially transparent. A target class label is selected. One or more objects of the first subset of images are relabeled with the target class label. In another embodiment, the class labels are removed from objects in the subset of images instead of relabeling them. Each of the first subset of images is overlaid with the partially transparent and scaled pixel pattern. The ML model is trained with the set of training images and the first subset of images to produce a trained and watermarked ML model.

Abstract: A circuit that includes a level shifter. The level shifter includes a shift path with two transistors coupled in series. The circuit also includes a GIDL detection circuit for detecting GIDL current conditions. The GIDL detection circuit generates a GIDL signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a transistor of the shift path to increase the conductivity of the transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least a portion of the shift path when the second transistor is nonconductive due to the level shifter being in a low power mode.