Abstract: Nested microstrip systems and methods, and systems and methods encompassing same, are disclosed herein. In one example, a nested microstrip system includes a printed circuit board (PCB) having first and second layer levels, where first and second conductive traces are positioned at the second layer level. The first conductive trace is configured to include an orifice, and to extend between first and second locations along a first path, and the second conductive trace is positioned within the orifice. A non-conductive gap portion of the orifice exists between the first and second conductive traces so that the second conductive trace is electrically isolated from the first conductive trace. One or more first electromagnetic signals can be propagated along a first part of the first conductive trace, and one or more second electromagnetic signals can be propagated along at least a second part of the second conductive trace.

Abstract: An apparatus and method for synchronously discharging multiple capacitive loads. In one embodiment, the apparatus includes first and second discharge circuits for discharging first and second capacitive loads, respectively. The apparatus also includes a control circuit coupled to the first and second discharge circuits and configured to control the second discharge circuit. The control circuit includes a first scaler circuit configured to generate a first scaled voltage based on a first voltage on the first capacitive load, a second scaler circuit configured to generate a second scaled voltage based on a second voltage on the second capacitive load, and a comparator circuit for comparing the first and second scaled voltages. The comparator circuit asserts a control signal when the second scaled voltage exceeds the first scaled voltage. The second discharge circuit discharges the second capacitive load when the comparator circuit asserts its control signal.

Abstract: Embodiments are provided for voltage regulators that include a first, a second, a third, and a fourth NMOS transistor cascoded between a high voltage source and a low voltage output; a resistor network including a first, a second, a third, and a fourth resistor connected in series between the high voltage source and ground, wherein gate electrodes of the second, third, and fourth NMOS are respectively connected to nodes between the first and second resistors, the second and third resistors, and the third and fourth resistors; and a multi-stage charge pump configured to provide a first bias voltage to a gate electrode of the first NMOS and a second bias voltage to the gate electrode of the second NMOS.

Abstract: An electronic device includes a digital circuit, a power delivery subsystem configured to provide a supply voltage and a body-biasing voltage to the digital circuit, and a controller a controller coupled to the power delivery subsystem. The controller is configured to determine a process parameter for the electronic device, determine a current temperature parameter for the electronic device, concurrently determine a first coarse-grain level for the supply voltage and a second coarse-grain level for the body-biasing voltage based on the process parameter, the current temperature parameter, and a frequency of a clock signal to be supplied to the digital circuit, and to determine a fine-grain level for the supply voltage.

Abstract: A receiver includes at least a first amplifier configured to receive a received signal and provide a first amplified signal based thereon, a mixer configured to receive the first amplified signal and provide an intermediate frequency signal based thereon and a second amplifier configured to receive the intermediate frequency signal and provide a second amplified signal based thereon. An automatic gain controller for the receiver is configured to, based on a first overload signal indicative of a first frequency range of the first amplified signal having one or more frequency components exceeding a first maximum signal power threshold and a second overload signal indicative of a second frequency range, narrower than the first, of the second amplified signal having one or more frequency components exceeding a second maximum signal power threshold, provide for control of a respective gain of one or both of the first amplifier and the second amplifier.

Abstract: A data processing system includes an SRAM array, wherein the plurality of SRAM cells provide a physically unclonable function (PUF). A PUF evaluation engine includes a selection circuit for selecting one or more word lines coupled to the plurality of SRAM cells in response to a challenge, and a cross-coupled latch coupled to two bit lines corresponding to two different SRAM cells of the plurality of SRAM cells. The cross-coupled latch is configured to provide one of two 2-bit values depending on which of the two bit lines discharges faster upon the two different SRAM cells being selected by the selection circuit, wherein the 2-bit value is part of a digital code provided in response to the challenge.

Abstract: Embodiments are provided for a method of operating a receiver system, the receiver system comprising one or more channels, the method comprising: monitoring a residual DC (direct current) offset in a present channel by sampling an output of an analog-to-digital converter (ADC) of the present channel; adjusting a DCO (direct current offset) correction signal that corresponds to the residual DC offset in response to an absolute value of the residual DC offset exceeding a programmable DCO threshold; and subtracting the DCO correction signal from an analog signal provided to the ADC to reduce the residual DC offset below the programmable DCO threshold.

Abstract: A circuit includes a transmitter circuit which includes a single-to-complementary circuit, a driver stage, and a pre-emphasis control circuit. The single-to-complementary circuit generates complementary output signals from a single ended input signal. The driver stage includes inputs to receive the complementary output signals, the driver stage includes a main driver circuit and a pre-emphasis driver circuit, and the pre-emphasis driver circuit is active during transitions of the complementary output signals to provide additional current for the driver stage. The pre-emphasis control circuit includes an RC pulse generation circuit in which the RC pulse generation circuit includes a capacitance and a resistance, and the RC pulse generation circuit provides, based on edges of a signal, pulses having a duration based on an RC time constant of the capacitance and resistance. The pre-emphasis driver circuit is active to provide additional current for the driver stage in response to the pulses.

Abstract: A capacitance-to-digital-converter includes a first delay block configured to output a first signal after a first delay based on a voltage at a capacitive sensor, the capacitive sensor configured to be iteratively discharged; a second delay block configured to output a second signal after a second delay; and a capacitance determination unit configured to determine a value indicative of a capacitance sensed by the capacitive sensor. This determination is based on: a number of clock periods during which the first delay is less than a third delay; a first time difference between receipt of the first signal and the second signal during a last clock period during which the first delay is less than the third delay; and a second time difference between receipt of the first signal and receipt of the second signal during a first clock period during which the first delay is greater than the third delay.

Abstract: A digitally controlled oscillator comprising a filtering digital to analogue converter, DAC, component and a voltage controlled oscillator, VCO, component comprising at least one control terminal arranged to receive a control voltage output by the DAC component; wherein the DAC component comprises a voltage generation component arranged to generate the control voltage and at least one configurable capacitive load component to which the control voltage is applied such that a filtering bandwidth of the DAC component is configurable by way of the at least one configurable capacitive load component.

Abstract: A processor includes an instruction pipeline. The pipeline can be operated alternatively in a multi-thread mode and in a single-thread mode. In the multi-thread mode, the instruction pipeline processes multiple threads in an interleaved or simultaneous manner. In the single-thread mode, the pipeline processes a single thread. The instruction pipeline comprises multiple functional units, each of which is reserved for one thread among the multiple threads when the pipeline is in the multi-thread mode and reserved for one context layer among multiple context layers when the instruction pipeline is in the single-thread mode.

Abstract: A technique for managing power in an embedded processing system includes generating a workload model for the embedded processing system in response to a control signal, an event status signal, and a reference clock signal. The control signal is received from a peripheral device. The event status signal is received from an event processor configured to control execution of tasks by a processor core of the embedded processing system. The technique includes providing power configuration information to the processor core. The power configuration information corresponds to an operating point selected based on the control signal, the event status signal, the reference clock signal, the workload model, and a predetermined energy model.

Abstract: Embodiments of a lead frame and packaged devices thereof, including a lead frame first and second rows of lead fingers respectively connected to first and second sides of the lead frame, the second side opposite the first side; a package body perimeter within which a package body of the packaged semiconductor device is formed; and a first die pad arm, wherein an end of the first die pad arm remains within the package body perimeter and is separated from the package body perimeter by a gap distance; wherein a first outermost lead finger of the first row of lead fingers is adjacent to the first die pad arm.

Abstract: A current-controlled oscillator receives an input current. Ramp voltage generating circuitry generates first and second ramp voltages in response to the input current. Selecting circuitry selects one of the first and second ramp voltages depending on their relative values. Switching circuitry receives a selected ramp voltage, generates a signal based on the selected ramp voltage relative to a reference voltage, and outputs a clock signal. In one embodiment, a comparator receives the reference voltage, one of the first and second ramp voltages, and outputs a comparison signal. Logic circuitry controls the ramp voltage generating circuitry to output one of the ramp voltages during one half of a clock cycle and to output the other ramp voltage during another half cycle of the clock signal based on the comparison signal and logic states of the logic circuitry.

Abstract: Embodiments of a method and a device are disclosed. A circuit can include a power factor corrector, wherein two or more desired input variables can be defined for the power factor corrector, and a processor that communicates with the power factor corrector, and which selects variables in the power factor corrector with respect to the two or more desired input variables defined for the power factor corrector. The two or more desired input variables can include a switching frequency and an input current and the variables can include an amount of operation in a conduction mode and at least one of a primary peak current and a primary conduction interval. The variables in the power factor corrector can be adapted to the two or more desired input variables to allow the power factor corrector to operate in an operating mode that can include the conduction mode.

Abstract: Embodiments of packaged semiconductor devices and lead frames for such devices are provided, such as a lead frame including: a row of lead fingers, wherein an outer end of each lead finger is connected to a leaded side of the lead frame; a package body perimeter that indicates placement of a package body of the packaged semiconductor device, wherein an inner end of each lead finger falls within the package body perimeter; a retention tab that protrudes from an interior edge of a non-leaded side of the lead frame, wherein the retention tab falls outside of the package body perimeter; and a non-conductive tie bar structure attached to the retention tab, wherein the non-conductive tie bar structure falls within the package body perimeter.

Abstract: This specification discloses methods and systems for implementing a chip integrated scope (i.e., chip scope (CS)), which is a feature that allows a user to scope RF signals (internally and externally to the DUT (device under test)), by using the RF receive path (including amplifier, filter, ADC, DSP) to capture and store signal traces. In some embodiments, this specification discloses methods and systems to enhance the resolution and accuracy of these signal traces by using raw and correction data for gain/phase compensation of gain/phase impairments introduced in the Rx (receiver) path. In some embodiments, the correction data is generated from one or more of the following: simulation data, characterization data, production test data.

Abstract: A power factor corrector circuit and a method of operating the power factor corrector circuit can include a power factor corrector, wherein two or more input variables can be defined for the power factor corrector including a peak current and an input current. A processor can select corresponding variables in the power factor corrector with respect to the two or more input variables defined for the power factor corrector, and the corresponding variables can include a peak current and an input current. The corresponding variables in the power factor corrector can adapt to the two or more input variables to allow the power factor corrector to operate in a conduction mode.

Abstract: A latch comparator which includes a preamplifier and a latch circuit. The preamplifier circuit operates amplification on a pair of differential input signals, and generates a pair of pre-amplified differential signals. The latch circuit receives the pre-amplified differential signals, compares the pair of pre-amplified differential signals, and generates a pair of latched comparison signals. The latch circuit includes a latch and a switch circuit. First and second input terminals of the latch receive the pre-amplified differential signals. The switch circuit includes a switch coupling between one of the first and second input terminals of the latch and the preamplifier circuit. The switch receives one of the pair of latched comparison signals as a control signal, and is switched in response to the one of the latched comparison signal.

Abstract: Embodiments of field effect transistor (FET) circuits, RF switches, and devices include source and drain terminals coupled to an active surface of a semiconductor substrate, a channel in the substrate between the source and drain terminals, and a plurality of gate structures coupled to the active surface over the channel. A channel contact is coupled to the active surface over the channel between a first pair of the gate structures, and a first capacitor is electrically coupled between the channel contact and a gate structure of the plurality of gate structures.