Abstract: Aspects of the disclosure are directed to compensating for errors in in an analog-to-digital converter circuit (ADC). As may be implemented in accordance with one or more embodiments, an apparatus and/or method involves an ADC that converts an analog signal into a digital signal using an output from a digital-to-analog converter circuit (DAC). A compensation circuit generates a compensation output by, for respective signal portions provided to the DAC, generating a feedback signal based on an incompatibility between the conversion of the signal portions into an analog signal and the value of the signal portions provided to the DAC. A compensation output is generated based on the signal input to the DAC with a gain applied thereto, based on the feedback signal.

Abstract: A method comprising: recording test code defined in a high-level test specification language; and automated analysis of the test code defined in the high-level test specification language before a conversion of the high-level test specification language to a low-level test implementation language configured to enable testing of a target by a test module.

Abstract: Processing of a data packet within a received wireless signal includes determining a frequency modulation (“FM”) domain carrier frequency offset (“CFO”) estimate component from a plurality of samples of the received wireless signal, determining a phase domain CFO estimate component from the plurality of samples of the received wireless signal, and determining a CFO estimation as a function of the FM domain CFO estimate component and the phase domain CFO estimate component. The data packet may be a Bluetooth Low Energy data packet. The FM domain CFO estimate component and the phase domain CFO estimate component may be determined from samples of a preamble field of the data packet.

Abstract: Embodiments of RF amplifiers and packaged RF amplifier devices each include a transistor with a drain-source capacitance that is relatively low, an input impedance matching circuit, and an input-side harmonic termination circuit. The input impedance matching circuit includes a harmonic termination circuit, which in turn includes a first inductance (a first plurality of bondwires) and a first capacitance coupled in series between the transistor output and a ground reference node. The input impedance matching circuit also includes a second inductance (a second plurality of bondwires), a third inductance (a third plurality of bondwires), and a second capacitance coupled in a T-match configuration between the input lead and the transistor input. The first and second capacitances may be metal-insulator-metal capacitors in an integrated passive device.

Abstract: A method of radar detection and a radar system for a motor vehicle are described. The radar system includes a transmitter for transmitting a radar signal having a time period, a plurality of receivers for receiving the transmitted radar signal reflected by an object, a signal compressor having a plurality inputs coupled to each of the receivers and at least one signal compressor output, the signal compressor being configured to compress the received signals to fewer output signals, each output signal having a number of samples. A signal re-constructor having at least one input coupled to each the signal compressor output and configured to determine a plurality signal strength values from the compressed signals, each signal strength value corresponding to a signal strength for a respective time-of-flight and angle-of-arrival value pair of a received signal. The radar system may detect an object with less memory and a lower power consumption while maintaining angular resolution.

Abstract: An embodiment of a semiconductor device includes a semiconductor substrate that includes a host substrate, a buffer layer that includes at least one additional layer formed over the substrate, a channel layer formed over the buffer layer, a barrier layer formed over the channel layer forming a channel, a gate electrode disposed over the substrate electrically coupled to the channel, and an ohmic contact recessed into the barrier layer. A method for fabricating the semiconductor device includes forming a semiconductor substrate that includes a mixed crystal layer, creating an isolation region that defines an active region along an upper surface of the semiconductor substrate, forming a gate electrode over the semiconductor substrate in the active region, and recessing an ohmic contact into the semiconductor substrate.

Abstract: Overmolded microelectronic packages containing knurled base flanges are provided, as are methods for producing the same. In various embodiments, the overmolded microelectronic package includes a molded package body, at least one microelectronic device contained in the molded package body, and a base flange to which the molded package body is bonded. The base flange includes, in turn, a flange frontside contacted by the molded package body, a device attachment region located on the flange frontside and to which the at least one microelectronic is mounted, and a knurled surface region. The knurled surface region includes a first plurality of trenches formed in the base flange and arranged in a first repeating geometric pattern. The molded package body extends or projects into the first plurality of trenches to decrease the likelihood of delamination of the molded package body from the base flange.

Abstract: Example antenna configured to be coupled to a first conductive structure having a first portion and a second portion, the antenna including: a second conductive structure having a first portion and a second portion; wherein the first portion of the second conductive structure is configured to be coupled to the first portion of the first conductive structure; a first feed point configured to be coupled to the second portion of the first conductive structure; wherein the first portion of the first conductive structure is configured to carry the RF signal current with a first current density; wherein the first portion of the second conductive structure is configured to carry the RF signal current with a second current density; wherein the first and second current densities are different.

Abstract: Embodiments of a substrate are provided herein, which include: a first metal plane and a second metal plane in a first metal layer, the first and second metal planes laterally separated by a first gap of dielectric material; and a third metal plane and a fourth metal plane in a second metal layer vertically adjacent to the first metal layer, the third and fourth metal planes laterally separated by a second gap of dielectric material, wherein the second gap comprises a first laterally-shifted gap portion and a second laterally-shifted gap portion, the first laterally-shifted gap portion is laterally offset from a vertical footprint of the first gap in a first lateral direction, and the second laterally-shifted gap portion is laterally offset from the vertical footprint of the first gap in a second lateral direction opposite the first lateral direction.

Abstract: A method and apparatus receive packets, wherein the packets comprise headers, and the headers comprise session parameter values, route the packets in response to the session parameter values matching an active traffic session entry of the active traffic session entries in an active traffic session cache memory, match the session parameter values against historical session entries in an historical session cache memory in response to the session parameter values not matching any active traffic session entry of the active traffic session entries in the active traffic session cache memory, wherein the historical session entries for traffic sessions in the historical session cache memory persist after the traffic sessions are no longer active, and, in response to the session parameter values not matching any historical session entry of the historical session entries in the historical session cache memory, performing a packet security check on the packets.

Abstract: The invention provides an apparatus and method which allows identification of the system which provided images for each pixel of a touchscreen display which displays merged images of arbitrary shapes supplied from a plurality of systems. It further allows routing of user inputs to the appropriate system for further processing. Colour keying may be used to superimpose one image onto another. The invention finds particular application in the automotive field where images produced by an infotainment system may be merged with those produced by a mobile phone onto the in-vehicle display screen.

Abstract: A passive keyless entry (PKE) system is disclosed. The PKE includes an in-vehicle apparatus. The in-vehicle apparatus includes a control unit that is configured to measure magnetic field and compute at least one angle between two projections of the magnetic field. When the measured angle is lower than a threshold value, an authorization signal is prevented.

Abstract: There is disclosed a synchronous digital circuit having a system clock and for processing a data signal, wherein the digital circuit comprises a data path, a hard macro having a macro input, a logic circuit in the data path upstream of the macro input and having a first part and a second part, the second part being immediately upstream of the macro input, a set-up timing error detector having an input, wherein the input is on the data path between the first part and the second part, and a timing correction unit, wherein the data transit time across the second part is equal to or less than one half of a clock period, and wherein the timing correction unit is configured to correct, in response to the set-up timing error detector detecting a set-up timing error, the detected set-up timing error before the data reaches the macro input.

Abstract: A switching amplifier circuit (200) connected to drive an impedance-based output load (230) includes high side and low side switches (201-204) configured and connected to connect first and second supply voltage lines to first and second output nodes (ANTP, ANTN) in response to gating control signals, and also includes an output current sensing circuit for measuring a current through the output load with a current sensing resistor (Rs) connected between the second supply voltage line and a source of one or more split gate-source switching transistors (203C) in the low side gate-source switching transistor, where a voltage sense circuit connected across the current sensing resistor is configured to sample a voltage across the current sensing resistor for measuring a sense current at the current sensing resistor.

Abstract: According to a first aspect of the present disclosure, a method for facilitating detection of one or more time series patterns is conceived, comprising building one or more artificial neural networks, wherein, for at least one time series pattern to be detected, a specific one of said artificial neural networks is built, the specific one of said artificial neural networks being configured to produce a decision output and a reliability output, wherein the reliability output is indicative of the reliability of the decision output. According to a second aspect of the present disclosure, a corresponding computer program is provided. According to a third aspect of the present disclosure, a corresponding system for facilitating the detection of one or more time series patterns is provided.

Abstract: A semiconductor structure includes a packaged semiconductor device having at least one device, a conductive pillar, an encapsulant over the at least one device and surrounding the conductive pillar, wherein the conductive pillar extends from a first major surface to a second major surface of the encapsulant, and is exposed at the second major surface and the at least one device is exposed at the first major surface. The packaged device also includes a conductive shield layer on the second major surface of the encapsulant and on minor surfaces of the encapsulant and an isolation region at the second major surface of the encapsulant between the encapsulant and the conductive pillar such that the conductive shield layer is electrically isolated from the conductive pillar. The semiconductor structure also includes a radio-frequency connection structure over and in electrical contact with the conductive pillar at the second major surface of the encapsulant.

Abstract: A frame delimiter detection system and method includes a phase differentiator and buffering module, a phase-to-I/Q reformatting module, a dot product module, an I/Q-to-polar reformatting module, a dot product comparison module, and a frame delimiter detection module. The method may include receiving in-phase and quadrature-phase (I/Q) formatted frequency domain input samples configured as a frame delimiter in a communication packet. An I/Q formatted dot product may be generated from the I/Q formatted frequency domain input samples and a reference pattern indicative of an expected frame delimiter. Further, a frame delimiter detection signal may be generated based on a magnitude of the I/Q formatted dot product.

Abstract: An electrically erasable programmable read only memory (EEPROM) emulation (EEE) system includes a non-volatile memory arranged to have a plurality of sectors in which each sector is arranged to have a plurality of record locations. A new record of new data is programmed into a record location of an active sector of the plurality of sectors. After successfully completing the programming of the new record, a number of failure-to-program (FTP) occurrences during the programming is compared to a first threshold. When the number of FTP occurrences is greater than the first threshold, a determination is made as to whether compression is needed, and in response to determining that compression is needed, the method includes selectively performing compression based on a second threshold.

Abstract: Molded air cavity packages and methods for producing molded air cavity packages are disclosed. In one embodiment, the molded air cavity package includes a molded package body having an upper peripheral edge portion, an air cavity around which the upper peripheral edge portion extends, and a cover piece bonded to the upper peripheral edge portion to enclose the air cavity. The cover piece has a lower peripheral edge portion, which cooperates with the upper peripheral edge portion to define a cover-body interface. The cover-body interface includes an annular channel extending around the cover-body interface, as taken about the package centerline, and first and second hardstop features formed on the upper peripheral edge portion of the molded package body and on the lower peripheral edge portion of the cover piece, respectively. The hardstop features contact to determine a vertical height of the annular channel, as taken along the package centerline.

Abstract: A Magnetic Random Access Memory (MRAM) array has a plurality of main MRAM bitcells and a plurality of canary MRAM bitcells in which a first Magnetic Tunnel Junction (MTJ) diameter of each of the main MRAM bitcells is larger than any second MTJ diameter of any of the canary bitcells. Test circuitry is configured to periodically poll the canary bitcells to determine if values stored at the canary bitcells match expected canary values. When the values do not match the expected canary values, the test circuitry is configured to indicate a presence of a magnetic field, and in response to determining the presence of the magnetic field, continue to poll the canary bitcells until the values match the expected canary values which indicates the magnetic field is no longer present.