Abstract: An amplifier module is provided. The amplifier module includes a multi-layer printed circuit board (PCB). A first power transistor die is mounted at a top surface of the multi-layer PCB. A second power transistor die is mounted at the top surface of the multi-layer PCB. An impedance inversion element is coupled between an output of the first power transistor die and an output of the second power transistor die. A combining node is formed at the output of the second power transistor die. A stub circuit including a transmission line element is coupled at the combining node.

Abstract: A method of making a semiconductor switch device. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type located adjacent the major surface. The method also includes depositing a gate dielectric on the major surface. The method further includes implanting ions into the first semiconductor region through a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region. The well region has a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on the gate dielectric to form a gate electrode located directly above the well region. The method further includes implanting ions into the first semiconductor region to form a source region and a drain region of the semiconductor switch device on either side of the gate electrode.

Abstract: An apparatus configured to, in respect of an electronic device comprising a battery for powering the electronic device and a charger configured to receive a mains power supply and, when connected to the electronic device, provide a power output to charge the battery, based on a determination of a failure of a request to increase the power output of the charger to the battery of the electronic device, the failure comprising where at least a requested increase of the power output of the charger by a first predetermined amount fails to yield an increase in the power output of the charger equal to the first predetermined amount within a threshold amount, provide an indication to the electronic device that the charger is disconnected from the mains power supply for causing the electronic device to indicate that the charger is disconnected from the mains power supply to a user of the electronic device.

Abstract: An output regulated charge pump including a low drop out (LDO) regulator configured to output a variable first output voltage, a multi-stage charge pump configured to receive the variable first output voltage and produce a second output voltage to power a load, a first feedback circuit configured to compare the second output voltage to a reference voltage, and a second feedback circuit configured to measure level of current used by the load, wherein the second feedback circuit outputs a level select signal to the LDO that is configured to vary a level of the first output voltage and reduce charge pump output ripple.

Abstract: A low dropout (LDO) regulator system is provided. The LDO regulator system includes a first amplifier circuit, a second amplifier circuit, and a switch circuit. The first amplifier circuit has a first input coupled to receive a reference voltage and an output. The second amplifier circuit has a first input coupled to the output of the first amplifier and is configured to provide a predetermined voltage at a first output. The switch circuit is coupled between the first output of the second amplifier circuit and a second input of the first amplifier circuit and is configured to cause an open circuit in a first feedback path from the first output of the second amplifier circuit to the second input of the first amplifier circuit based on a control signal.

Abstract: One example discloses a first wireless communication device, including: a first near-field transceiver and a first far-field transceiver; wherein the first wireless communication device is configured to communicate with a second wireless device having a second near-field transceiver and a second far-field transceiver; wherein the first near-field transceiver is configured to communicate with the second near-field transceiver; wherein the first far-field transceiver is configured to communicate with a third wireless device in a far-field frequency bandwidth; wherein the second far-field transceiver is configured to communicate with a fourth wireless device in the far-field frequency bandwidth; and wherein communications between the first wireless device and the third wireless device interfere beyond a threshold interference level with communications between the second wireless device and the fourth wireless device unless the first and second wireless devices are at least partially screened by a conductive host

Abstract: A method for testing a multi-axis micro-electro-mechanical system(MEMS) acceleration sensor includes applying a first voltage to a first-axis excitation plate to move a first proof mass in contact with a proof mass stop. A second voltage is applied to a second-axis excitation plate while maintaining the first voltage to the first-axis excitation plate, to move the first proof mass in a direction orthogonal to the first-axis while in contact with the proof mass stop A reference voltage is applied to the first-axis excitation plate and a determination is made whether an output voltage of the MEMS device is higher than a threshold voltage. If the output voltage is higher than the threshold voltage ten stiction is detected and stiction recovery may therefore be preformed.

Abstract: One example discloses a near-field device, configured to receive a non-propagating quasi-static near-field signal from a near-field antenna, comprising: a tuning circuit including a set of impedance tuning banks; and a controller configured to, identify a set of impedance values for the impedance tuning banks corresponding to an initial resonance frequency, bandwidth and/or quality factor of the near-field antenna and near-field device combination; detect a change in the resonance frequency, bandwidth and/or quality factor; access a pre-stored set of specific resonance frequency, bandwidth and/or quality factor changes corresponding to a set of specific conductive structures; identify a conductive structure from the set of conductive structures corresponding to the detected change; access a pre-stored set of specific near-field device actions corresponding to the set of conductive structures; and effect a set of specific actions from the set of near-field device actions corresponding to the identified conduct

Abstract: A memory controller is used to verify authenticity of data stored in a first memory unit, and includes a secure memory unit which stores a pre-stored value representative of the authenticity of the data to be written in the first memory unit. A processing system calculates a value representative of the data in the first memory unit after a write cycle. The calculation of the calculated value is triggered by the write cycle. The calculated value is compared with the pre-stored value to verify whether the data stored in the first memory unit after the write cycle has been altered in accordance with the authenticity. By comparing the calculated value with the pre-stored value, authenticity of the data stored in the first memory unit after the write cycle is verified, thus preventing the memory controller from operating if the data written to the first memory unit is not authentic.

Abstract: Apparatus for generating electric power within vicinity of powerlines using varying electric fields and an electrical pathway to ground are disclosed. Such apparatus preferably include, for example, UAVs, charging stations, and power strips mountable to a powerline transmission tower. Methods and systems utilizing such apparatus further are disclosed. The electrical pathway to ground may include an interface that is tethered to a UAV and that is dragged along a shield wire behind the UAV as the UAV travels along the powerlines. The electrical pathway to ground alternatively may include an electrical connection to a ground of a support structure of the powerlines when the apparatus is a power strip mounted to the support structure.

Abstract: A method, system, program control code, and hardware circuit are provided for predicting performance of an system-on-chip (SoC) (100) having a processor (105) and a master device (106) having shared access to a single-port memory (104) by activating a timer (102) in a Performance Monitoring Unit (PMU) (101) to measure a specified number of cycles of the processor in a defined measure instance and by activating a memory access counter (103) in the PMU to measure a first count of memory access requests to the single-port memory by the processor in the defined measure instance and to measure a second count of memory access requests to the single-port memory by the master device in the defined measure instance, so that the first and second counts are stored in memory.

Abstract: A switched-capacitor gain stage circuit and method include an amplifier connected to an input sampling circuit with sampling switched capacitors for coupling an input voltage and a first or second reference voltage to one or more central nodes during a sampling phase and for coupling the one or more central nodes to an amplifier input during a gain phase, wherein a reference loading circuit uses a plurality of sampling switched capacitors connected in a switching configuration to selectively couple a first reference voltage and/or a second reference voltage to the central node by pre-charging the plurality of sampling switched capacitors with the first and second reference voltages during the sampling phase, and by coupling each of the first and second reference voltages to at least one of the plurality of sampling switched capacitors when connected to the central node during the gain phase.

Abstract: A method of calculating the x-coordinate(xM) of a point mapping in an elliptic curve Diffie-Hellman key exchange protocol (EC-DHKF), wherein the point mapping is defined as sG+H, where sG is a point (xS,yS) on an elliptic curve and H is a point (xH,yH) on the elliptic curve, including: computing V=yS2 based upon the elliptic curve and xS; computing W=yH2 based upon the elliptic curve and xH; computing U=sqrt(W·V)mod p, where p is a large prime number; choosing U?=U or U?=p?U such that U? based upon a characteristic agreed upon by the parties to the EC-DHKF; computing xM based upon V, W, U?, xS, xH, and p.

Abstract: A runtime security system, including: a shared core configured to execute processes having varying levels of trustworthiness configured to receive security services requests; an execution monitor configured to monitor the execution of the shared core further comprising a timer, a policy table, and an execution monitor state machine; secure assets including cryptographic keys; and immutable security service functions configured to enable access to the secure assets in response to secure services requests; wherein the execution monitor is configured to: detect that the shared core has received a secure boot request; verify that the secure boot request is valid; allow the shared core to securely boot when the secure boot request valid.

Abstract: A method is provided for secure firmware provisioning of a device. In the method, an integrated circuit (IC) is manufactured by a first entity for use in the device. The IC is provided to a second entity for manufacturing the device using the IC. The IC has a unique identifier (UID) and secret key derivation data (KDD). A secure memory is provided to a third entity. The secure memory has a first key pair, and the secure memory is used with a firmware provisioning toolchain of the second entity. During manufacturing of the device by the second entity, the secure memory is enabled to verify the IC by verifying the UID. The secure memory stores a firmware decryption key, and is enabled to encrypt the firmware decryption key. The encrypted firmware decryption key is then provided to the IC, and the IC decrypts the encrypted firmware decryption key for use by the IC in decrypting the firmware.

Abstract: A hardware interface component arranged to operably couple at least one arithmetic unit to a an interconnect component of a processing system. The hardware interface component comprises a plurality of program-visible registers and at least one operation decoder component. The at least one operation decoder component is arranged to, upon receipt of a write access request via the interconnect component corresponding to a decorated memory-mapped address range for the hardware interface component, decode a register identifier component of a target address of the received write access request to identify at least one of the program-visible registers, decode a decoration component of the target address of the received write access request to identify an arithmetic operation to be performed, and configure the arithmetic unit to perform the identified arithmetic operation on at least one input operand within the identified at least one program-visible register.

Abstract: Self-configured, power-aware circuitry configured to enhance power efficiency within integrated circuitry by self-calibrating the power consumption utilized within the integrated circuitry according to the requirements of an application program running within the integrated circuitry. The power consumption is self-calibrated within the integrated circuitry on a per application-based manner so that the integrated circuitry can be implemented with a plurality of various generalized functionalities, each of which may or may not be utilized while a specific application program is running within the integrated circuitry. Power consumption within the integrated circuitry is reduced by independently and dynamically controlling multiple power sections delineated within the integrated circuitry.

Abstract: According to a first aspect of the present disclosure, a fingerprint sensing system is provided, comprising: a sensing unit configured to measure a physical property of a sensing cell and to produce a voltage in dependence on said physical property; and an analog-to-digital converter configured to convert said voltage into a digital signal, wherein said analog-to-digital converter implements a non-linear conversion function. According to a second aspect of the present disclosure, a corresponding fingerprint sensing method is conceived. According to a third aspect of the present disclosure, a corresponding computer program product is provided.

Abstract: High thermal performance microelectronic modules containing sinter-bonded heat dissipation structures are provided, as are methods for the fabrication thereof. In various embodiments, the method includes the steps or processes of providing a module substrate, such as a circuit board, including a cavity having metallized sidewalls. A sinter-bonded heat dissipation structure is formed within the cavity. The sintered-bonded heat dissipation structure is formed, at least in part, by inserting a prefabricated thermally-conductive body, such as a metallic (e.g., copper) coin into the cavity. A sinter precursor material (e.g., a metal particle-containing paste) is dispensed or otherwise applied into the cavity and onto surfaces of the prefabricated thermally-conductive body before, after, or concurrent with insertion of the prefabricated thermally-conductive body.

Abstract: An area-efficient, low voltage ESD protection device (200) is provided for protecting low voltage pins (229, 230) against ESD events by using one or more stacked low voltage NPN bipolar junction transistors, each formed in a p-type material with an N+ collector region (216) and P+ base region (218) formed on opposite sides of an N+ emitter region (217) with separate halo extension regions (220-222) formed around at least the collector and emitter regions to improve the second trigger or breakdown current (It2) and set the snapback voltage (Vsb) and triggering voltage (Vt1) at the desired level.