Abstract: A digital synthesizer includes a ramp generator that generates a signal of frequency control words, FCW, that describes a desired frequency modulated continuous wave; a digitally controlled oscillator, DCO, that receives the FCW signal and outputs a DCO signal; and a feedback loop that includes a dual time-to-digital converter, TDC, circuit to measure a delay between a representation of the DCO signal and a reference signal. The TDC circuit comprises a medium-resolution TDC circuit coupled to a fine-resolution TDC circuit; and a phase comparator coupled to the ramp generator that compares a phase of the FCW signal output from the ramp generator and a signal fed back from the DCO via the feedback loop and output a N-bit oscillator control signal. The medium-resolution TDC circuit comprises a plurality of individual delay cells, where each of the plurality of individual delay cells is coupled to a respective individual fine-resolution TDC circuit.

Abstract: An integrated circuit includes an output driver circuit configured to provide a first voltage at an output terminal. The output driver circuit includes a transistor having a first current electrode coupled at a voltage supply terminal and a second current electrode coupled at the output terminal, and a resistor having a first terminal coupled at the output terminal and a second terminal coupled at a first node. An amplifier circuit is coupled to the output driver circuit and is configured to generate a proportional to absolute temperature (PTAT) current in a first circuit branch of the output driver circuit coupled at the first node. A complementary to absolute temperature (CTAT) circuit is configured to generate a CTAT current in a second circuit branch coupled at the first node.

Abstract: A loop-filter comprising: a first-integrator, and one or more further-integrators. The first-integrator is an active-RC integrator, and comprises a first-integrator-input-terminal configured to receive: (i) an input-signal, and (ii) a feedback-signal; a first-integrator-first-output-terminal configured to provide a first-integrator-first-output-signal; and one or more first-integrator-further-output-terminals. Each of the one or more further-integrators is a Gm-C integrator, and they are connected in series between the first-integrator-first-output-terminal and a loop-filter-output-terminal. For a first further-integrator in the series, the further-integrator-input-terminal is configured to receive the first-integrator-first-output-signal. For any subsequent further-integrators in the series, the further-integrator-input-terminal is configured to receive: (i) the further-integrator-output-signal from the preceding further-integrator in the series; and (ii) one of the first-integrator-further-output-signals.

Abstract: An audio processor is described. The audio processor includes a sensor input; an audio input for receiving an audio input signal; an audio output for outputting an audio signal to a loudspeaker. The audio processor is configured to determine a parameter value representative of temperature from a sensor signal received on the sensor input; process a received audio input signal by increasing the audio signal power in response to the temperature being below a predetermined threshold; and output the processed audio signal on the audio output.

Abstract: An electrostatic discharge (ESD) protection device includes a first bi-directional silicon controlled rectifier having a doped well of a first conductivity type, a buried doped layer having a second conductivity type opposite the first conductivity type, first and second highly doped regions of the second conductivity type in the doped well, and a third highly doped region of the first conductivity type in the doped well. The first, second and third highly doped regions are connected to a first node. A first transistor in the doped well includes an emitter coupled to the first highly doped region, a collector coupled to a conductive line in the buried doped layer, and a base coupled to the third highly doped region. A second transistor in the doped well includes an emitter coupled to the second highly doped region, a collector coupled to the conductive line in the buried doped layer, and a base coupled to the third highly doped region.

Abstract: A low-leakage circuit including a switch having an input node, gate, bulk region, and pin node, a comparison circuit configured to determine and output a greater of two voltages of the switch, a latching circuit connected to the comparison circuit and configured to bias the gate and the bulk region of the switch using the greater of the two voltages, and a shorting circuit configured to control a voltage at the bulk region to ensure that no leakage current flows from the pin node.

Abstract: A UAV in which electric power is generated for an electric load from differentials in electric field strengths within a vicinity of powerlines includes: a plurality of electrodes separated and electrically insulated from one another for enabling differentials in voltage resulting from differentials in electric field strength experienced thereat; and electrical components electrically connected therewith and configurable to establish one or more electric circuits whereby voltage differentials causes a current to flow through the established electric circuit for powering an electric load. Preferably, the UAV includes a control assembly having one or more voltage-detector components configured to detect relative voltages of the electrodes; and a processor enabled to configure—based on the detected voltages and based on voltage and electric current specifications for powering the electric load—one or more of the electrical components to establish an electric circuit for powering the electric load.

Abstract: A FinFet capacitor structure includes a first, second, third, and fourth FinFet fin, a contiguous gate layer over the fins, first and second source/drain contacts in direct physical contact with the first FinFet fin on either side of the gate layer, a first gate contact in direct physical contact with a portion of the contiguous gate layer directly over the second FinFet fin, third and fourth source/drain contacts in direct physical contact with the third FinFet fin on either side of the gate layer, and a second gate contact in direct physical contact with a portion of the contiguous gate layer directly over the fourth FinFet fin. The first, second, third, and fourth source/drain contacts are all connected to a first power supply rail, and the first and second gate contacts are all connected to a second power supply rail.

Abstract: A processing system includes a data processor, an input, an output, a memory, an operation parser, and a timer manager instance controller. The input receives create-timer-manager-instance (CTMI) commands identifying a number of timers supported by a timer manager instance. The output provides responses including a CTMI response associated with the CTMI command. The operation parser receives the CTMI command from the input. The timer manager instance controller receive a control input from the operation parser based upon the CTMI command, and in response, allocates a block of memory locations in the memory based on the number of timers and provides a CTMI response to the output to indicate that the CTMI response was executed by the timer manager instance controller.

Abstract: An electric power meter for measuring electric power is provided. The power meter has a frequency domain converter arranged to convert a sequence of digital voltage samples from the time domain to a frequency domain obtaining digital voltage frequency components, and to convert a sequence of digital current samples from the time domain to the frequency domain obtaining digital current frequency components. The electric power meter also has a frequency domain correction unit arranged to correct the voltage frequency components and the current frequency components by multiplying at least one frequency component of the current frequency components and the voltage frequency components with a complex correction factor using a complex multiplication unit. Electric power is computed by an energy calculation unit.

Abstract: Peer-to-peer type communications are facilitated in a secure communication device. As consistent with one or more example embodiments, near-field communications are effected (150, 152) using a secure payment protocol conforming to a predefined certification standard for the secure payment protocol (100). Communication operability is transmitted (152) under the secure payment protocol and used to identify other protocols/applications under which communications can be effected. This information is used to effect P2P protocol communications (160), where applicable, and to do so while complying with the secure payment protocol.

Abstract: A system on chip, comprising a processing unit for executing processes, a memory unit, and a memory control unit connected between the processing unit and the memory unit, is described. The memory control unit allocates a memory region to a process. The memory control unit comprises a process activity counter which counts a duration of the process or transactions by the process to or from the memory region and which maintains a process activity count representing the counted duration of the process or the counted transactions to or from the memory region. The memory control unit disables the memory region in response to the process activity count exceeding a maximum process activity count. Notably, it blocks the memory region against further transactions by the process and against transactions by any other processes. A method of operating a system on chip is also described.

Abstract: A method, system, and architecture (100) for adaptively field testing for hardware faults on an integrated circuit device includes a central quality assurance server (121) which receives specified hardware metric data (131) monitored at an integrated circuit device (110) in the field, identifies prioritized built-in self-test (BIST) fault detection tests (134) based on the specified hardware metric data, securely downloads the prioritized BIST fault detection tests (132) to the integrated circuit device for execution to identify a first hardware fault at the integrated circuit device, and then receives diagnosis information (133) identifying the first hardware fault from the integrated circuit device which is used to update the prioritized BIST fault detection tests.

Abstract: One example discloses a wireless device, comprising a near-field transceiver configured to be coupled to a host structure; a controller coupled to the transceiver; wherein the near-field transceiver includes a feed point configured to be coupled to a conductive surface; wherein the conductive surface is configured to be capacitively coupled to the host structure to form part of a near-field electric antenna; and wherein the conductive surface is configured to be in repeated, but not continuous, contact with a ground.

Abstract: A detector (110) detects an unwanted oscillation generated by a closed-loop system (112) due to disconnection, improper usage, or absence of a stability-controlling element (104) necessary for the closed-loop system to function properly. An integrated circuit (102) includes the closed-loop system, the detector, and a supervisory system (114) that disables the closed-loop system upon disconnection of the stability-controlling element from the closed-loop system.

Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to first connectivity circuitry by a first processor bus and configured to provide first bus transactions to the first processor bus, the discrete signal lines connected to the first connectivity circuitry to provide first discrete signals indicative of discrete events, the first connectivity circuitry configured to store the first discrete signals in a plurality of virtual signal registers and to convert the first bus transactions and the first discrete signals into die-to-die message packets to be communicated to the second connectivity circuitry via a die-to-die interconnect between the first die and the second die, the first discrete signals being converted into the die-to-die message packets on a register-by-register basis.

Abstract: In accordance with a preferred embodiment, a charging station for charging of a UAV within a vicinity of powerlines includes an interface for electric coupling with the UAV for charging of a rechargeable battery of the UAV; a power supply having first and second electrodes separated and electrically insulated from each other for enabling a differential in voltage at the first and second electrodes resulting from a differential in electric field strength experienced at the first and second electrodes when within the vicinity of the powerlines; and electrical components electrically connected with the first and second electrodes and configured to establish a circuit with the rechargeable battery of the UAV when electronically coupled with the interface. The differential in voltage between the first and second electrodes causes electric current to flow through the electric circuit for charging the battery of the UAV.

Abstract: A system and method wherein die-to-die communication are provided between a first die and a second die contained in a common integrated circuit (IC) package, a first processor on the first die communicatively coupled to the first connectivity circuitry by the first processor bus and configured to provide first bus transactions, to be provided to the second connectivity circuitry, to the first processor bus, the first connectivity circuitry configured to utilize a multiple simultaneous outstanding transaction capability supporting multiple simultaneous outstanding write transactions concurrent with multiple simultaneous outstanding read transactions, the second connectivity circuitry configured to provide processor bus flow control information and elasticity buffer status information pertaining to the elasticity buffer to the first connectivity circuitry via a common message for flow control.

Abstract: A baseband amplifier circuit comprising a single-ended to differential converter followed by at least one boosted follower amplifier. The boosted follower amplifier comprises a first transconductance device arranged to control a first current between a first supply node and a first output node in response to a voltage at a first input node, a second transconductance device arranged to control a second current between the first output node and a second supply node in response to a voltage at a second input node, a third transconductance device arranged to control a third current between the first supply node and a second output node in response to a voltage at a third input node, and a fourth transconductance device arranged to control a fourth current between the second output node of the boosted follower amplifier and the second supply node in response to a voltage at a fourth input node.

Abstract: A system for register error detection is described, the system comprising: a plurality of addressable registers comprising sets of registers, the registers in each set having contiguous addresses; a cyclic redundancy check generator coupled to the addressable registers and configured to determine a cyclic-redundancy-check result for each set of registers from the values of each of the respective set of registers; a controller coupled to the registers and the cyclic-redundancy-check generator.