Patents Assigned to NXP
  • Method and system for automatic power control (APC) in a communications device that communicates via inductive coupling
    Patent number: 10461811
    Abstract: Embodiments of methods and systems for automatic power control (APC) in a communications device that communicates via inductive coupling are described. In an embodiment, a method for APC in a communications device that communicates via inductive coupling involves obtaining multiple system parameters, determining an APC configuration of the communications device from the system parameters, and controlling a transmission configuration of the communications device based on the APC configuration. Other embodiments are also described.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: October 29, 2019
    Assignee: NXP B.V.
    Inventors: Gernot Hueber, Ian Thomas Macnamara
  • Platoon control
    Patent number: 10459454
    Abstract: A method and apparatus are provided for controlling a vehicle travelling in a platoon. A first set of information is received at a first vehicle in a platoon, the first set of information relating to at least one other vehicle in the platoon. One of a plurality of control algorithms is selected in dependence on the first set of information, wherein each of the plurality of control algorithms correspond to a respective platoon communication topology. The first vehicle is controlled in response to the first set of information and the selected one of the control algorithms.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: October 29, 2019
    Assignee: NXP B.V.
    Inventors: Apoorva Saxena, Hong Li, Dip Goswami
  • Dual-interface IC card module
    Patent number: 10461057
    Abstract: The disclosure relates to a dual-interface integrated circuit (IC) card module for use in a dual-interface IC card. Embodiments disclosed include a dual-interface integrated circuit card module (150), the module comprising: a substrate (104) having first and second opposing surfaces; a contact pad (102) on the first surface of the substrate; an integrated circuit (110) on the second surface of the substrate (104), the integrated circuit (110) having electrical connections to the contact pad (102) through the substrate (104); and a pair of antenna pads (108) disposed in recesses (103) in the second surface of the substrate (104) and electrically connected to corresponding antenna connections on the integrated circuit (110).
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: October 29, 2019
    Assignee: NXP B.V.
    Inventor: Christian Zenz
  • Network node and method for identifying a node in transmissions between neighbouring nodes of a network
    Patent number: 10455584
    Abstract: A network node for a wireless network comprises a processor, a memory and an antenna. The network node is operable to generate a random or pseudo-random number and to assign said number as an address for identifying said node to other nodes in said network.
    Type: Grant
    Filed: August 8, 2017
    Date of Patent: October 22, 2019
    Assignee: NXP B.V.
    Inventor: Petr Kourzanov
  • Memory array with read only cells having multiple states and method of programming thereof
    Patent number: 10453544
    Abstract: A read only memory (ROM) having a first row of ROM cells, a first conductive line along the first row of ROM cells, and a second conductive line along the first row of ROM cells. The ROM cells of the first row of ROM cells are selectively coupled during programming to the first conductive line and the second conductive line so that in a first mode of the ROM the first row of ROM cells provide a first combination of logic highs and logic lows and in a second mode of the memory the first row of ROM cells provide a second combination of logic highs and lows independent of the first combination of logic highs and logic lows.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: October 22, 2019
    Assignee: NXP USA, INC.
    Inventors: Jianan Yang, Brad J. Garni, Shayan Zhang
  • Charge pump overshoot prevention for gate drivers
    Patent number: 10454360
    Abstract: An over-voltage protection circuit and method may include a pass gate and a voltage boosting circuit for providing protection to start-up voltage-sensitive circuits during start-up conditions of a system including the voltage-sensitive circuits. The pass gate may include a drain, source, and gate, with the drain configured to receive an input signal and the source configured to output the input signal, in response to a pass gate driving voltage signal applied to the gate of the pass gate. The voltage boosting circuit may include an output coupled to the gate of the pass gate, the voltage boosting circuit configured to generate a pass gate driving voltage on the output. The voltage boosting circuit further configured to passively control the pass gate driving voltage to a level less than a steady-state voltage level during start-up of the protection circuit.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 22, 2019
    Assignee: NXP USA, INC.
    Inventors: Ahmad Dashtestani, Siamak Delshadpour
  • Boost control signal generator
    Patent number: 10454424
    Abstract: A method and operates for generating a boost control signal for a DC-DC-booster is described. An audio signal may be received comprising a plurality of audio sample values. The audio signal may be delayed for a delay time. A maximum-delayed-value of the audio sample values during the delay time may be determined. The boost control signal may be generated from the maximum of the non-delayed audio signal sample value and the maximum-delayed-value.
    Type: Grant
    Filed: August 31, 2018
    Date of Patent: October 22, 2019
    Assignee: NXP B.V.
    Inventors: Maarten van Dommelen, Frédéric Chalet, Benno Krabbenborg
  • Signal processor
    Patent number: 10453469
    Abstract: A signal processor comprising: a modelling block, configured to receive a frequency-domain-input-signal, a fundamental-frequency-signal representative of a fundamental frequency of the frequency-domain-input-signal; and configured to provide a pitch-model-signal based on a periodic function, the pitch-model-signal spanning a plurality of discrete frequency bins, each discrete frequency bin having a respective discrete frequency bin index, wherein within each discrete frequency bin the pitch-model-signal is defined by: the periodic function; the fundamental frequency; the frequency-domain-input-signal; and the respective discrete frequency bin index. The signal processor further comprises a manipulation block, configured to provide an output-signal based on the frequency-domain-input-signal and the pitch-model-signal.
    Type: Grant
    Filed: March 26, 2018
    Date of Patent: October 22, 2019
    Assignee: NXP B.V.
    Inventors: Nilesh Madhu, Wouter Joos Tirry
  • Controller area network (CAN) device and method for emulating classic CAN error management
    Patent number: 10452504
    Abstract: Embodiments of a device and method are disclosed. In an embodiment, a CAN device is disclosed. The CAN device includes a transmit data (TXD) input interface, a TXD output interface, a receive data (RXD) input interface, an RXD output interface and a traffic control system connected between the TXD input and output interfaces and between the RXD input and output interfaces. The traffic control system is configured to detect the presence of classic CAN traffic on the RXD input interface and if the presence of classic CAN traffic is detected on the RXD input interface, emulate an error management protocol of a classic CAN controller in response to signals received on the TXD input interface.
    Type: Grant
    Filed: August 15, 2014
    Date of Patent: October 22, 2019
    Assignee: NXP B.V.
    Inventors: Bernd Elend, Matthias Muth
  • Digitally controlled oscillator with temperature compensation
    Patent number: 10454482
    Abstract: A device comprising: a voltage reference supply, configured to provide a reference voltage that varies in response to temperature according to a predefined relationship; a temperature sensor providing a temperature signal indicating a temperature; a first controller configured to receive the temperature signal and to output a control signal; an LC-DCO receiving the reference voltage and providing an output signal with a frequency from an LC circuit, the LC-DCO comprising a switched capacitor bank configured to provide temperature compensation by varying an effective capacitance in the LC circuit in response to the control signal.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: October 22, 2019
    Assignee: NXP USA, Inc.
    Inventors: Cristian Pavao Moreira, Didier Salle, Olivier Vincent Doare, Birama Goumballa
  • Data processing system having dynamic thread control
    Patent number: 10445133
    Abstract: A method for managing thread execution in a processing system is provided. The method includes setting a first watchpoint, and generating a first watchpoint trigger corresponding to the first watchpoint. In response to the first watchpoint trigger, execution of a first thread is controlled in accordance with a value stored in a first control register. Controlling the first thread may further include disabling execution of the first thread. The disabling execution of the first thread may occur within the first watchpoint region.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: October 15, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jonathan J. Gamoneda, Jehoda Refaeli, Jeffrey W. Scott
  • Reciprocal approximation circuit
    Patent number: 10447983
    Abstract: A reciprocal approximation circuit has a first iteration circuit for generating an approximate reciprocal value of an operand. The operation of the first iteration circuit is controlled by two bits of the operand, which indicate a range in which the operand lies. The first iteration circuit uses hardware friendly initial values based on the two bits for generating the approximate reciprocal value. The reciprocal approximation circuit does not require any additional circuit for selecting an initial value for the first iteration circuit.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 15, 2019
    Assignee: NXP USA, INC.
    Inventor: Mahesh Chandra
  • Sensor system and sensing method
    Patent number: 10444268
    Abstract: In accordance with a first aspect of the present disclosure, a sensor system comprising a processing unit and an array of sensor elements, wherein the processing unit is configured to: identify mutually different sets of sensor elements within the array and step sequentially through said sets; identify mutually different subsets of sensor elements within said sets and step sequentially through said subsets; concurrently sample the sensor elements within said subsets. In accordance with a second aspect of the present disclosure, a corresponding sensing method is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.
    Type: Grant
    Filed: April 3, 2018
    Date of Patent: October 15, 2019
    Assignee: NXP B.V.
    Inventor: Thomas Suwald
  • Memory system having a source bias circuit
    Patent number: 10446225
    Abstract: A memory system includes an isolated first well of a first polarity and an array of volatile memory cells. Each of the memory cells includes a first set of transistors in the isolated first well, and a second set of transistors. A source bias circuit is coupled to the array of volatile memory cells. At least a portion of the source bias circuit is in the isolated first well and coupled to source electrodes of the first set of transistors of each of the memory cells. A control circuit is configured to enable the source bias circuit.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: October 15, 2019
    Assignee: NXP USA, Inc.
    Inventors: Alexander Hoefler, Nihaar N. Mahatme
  • Radio frequency (RF) receiver circuit
    Patent number: 10447206
    Abstract: An integrated circuit includes a first high-pass filter having an input coupled to receive a first signal and an output coupled to a first input of a first differential pair of transistors. A second high-pass filter includes an input coupled to receive a second signal and an output coupled to a second input of the first differential pair of transistors. The second signal may be a complementary signal of the first signal. A second differential pair of transistors includes control electrodes coupled to a first voltage supply terminal. A boost circuit is coupled between the second differential pair of transistors and the first voltage supply terminal. A low-pass filter is coupled between the first differential pair of transistors and the second differential pair of transistors.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: October 15, 2019
    Assignee: NXP USA, INC.
    Inventors: Jaeyoung Lee, Nader Rohani
  • System and method allowing for determining relative positions of slave units along a stub bus
    Patent number: 10447550
    Abstract: The present application relates to a system and a method for determining relative positions slave units along a stub bus with at least a power line and a ground line. Each slave unit is operable in different power modes, which are differentiated by effective resistances between the power and ground lines. A reference voltage potential drop is determined for each slave unit while the slave units are operating in a first power mode. A positioning voltage potential drop is determined for one or more slave units while a selected slave unit is operating in a second power mode. Relative positions of the slave units are determined based on the relative voltage potential drops obtained from the reference and positioning voltage potential drops.
    Type: Grant
    Filed: March 25, 2018
    Date of Patent: October 15, 2019
    Assignee: NXP B.V.
    Inventors: Arnoud Pieter van der Wel, Joop Petrus Maria van Lammeren, Luc van Dijk
  • Non-volatile random access memory (NVRAM)
    Patent number: 10446608
    Abstract: A semiconductor device and methods for making the same are disclosed. The device may include: a first transistor structure; a second transistor structure; a capacitor structure comprising a trench in the substrate between the first and second transistor structures, the capacitor structure further comprising a doped layer over the substrate, a dielectric layer over the doped layer, and a conductive fill material over the dielectric layer; a first conductive contact from the first transistor structure to a first bit line; a second conductive contact from the second transistor to a non-volatile memory element; and a third conductive contact from the non-volatile memory element to a second bit line.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: October 15, 2019
    Assignee: NXP USA, INC.
    Inventor: Anirban Roy
  • Power management circuit
    Patent number: 10447068
    Abstract: One example discloses a power management circuit, wherein the power management circuit is configured to cause a device to be operated at a first power level and a second power level. The circuit includes: an RF transmitter configured to generate an RF signal having a set of transmitted RF signal attributes; an RF receiver configured to detect the RF signal having a set of received RF signal attributes; and a proximity detection circuit configured to transition the device from the first power level to the second power level in response to a preselected difference between the transmitted set of RF signal attributes and the received set of RF signal attributes.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: October 15, 2019
    Assignee: NXP B.V.
    Inventors: Ferdinand Jacob Sluijs, Marcel Wilhelm Rudolf Martin van Roosmalen
  • Method and system for bidirectional communication
    Patent number: 10445268
    Abstract: Methods for bidirectional communication and bidirectional communication buffers are described. In one embodiment, a method for bidirectional communication using first and second communication buses, which have opposite directions of data transmission, is described. The method for bidirectional communication involves detecting a signal from a first communication bus and buffering the detected signal and transmitting the buffered signal through a second communication bus while blocking data transmission from the second communication bus. Other embodiments are also described.
    Type: Grant
    Filed: April 29, 2016
    Date of Patent: October 15, 2019
    Assignee: NXP B.V.
    Inventors: Jinxi Yan, Shuiwen Huang, Tinghua Yun
  • Low supply linear equalizer with programmable peaking gain
    Patent number: 10447507
    Abstract: Embodiments of linear equalizers are disclosed. In an embodiment, a linear equalizer includes sets of transistors, a resistor, and first and second impedance elements. The sets of transistors are connected between at least one input terminal of the linear equalizer and at least one output terminal of the linear equalizer. The resistor is connected to a supply voltage, to the at least one output terminal, and to the sets of transistors. The first and second impedance elements are connected between emitter terminals or source terminals of the sets of transistors and at least one fixed voltage. A peaking gain of the linear equalizer is programmable by adjusting a direct current (DC) component of at least one input signal that is received at the at least one input terminal and that is applied to the sets of transistors.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: October 15, 2019
    Assignee: NXP B.V.
    Inventors: Xu Zhang, Soon-Gil Jung, Ahmad Yazdi