Abstract: One example discloses an antenna combination device, comprising: a modulation unit; wherein the modulation unit is configured to be coupled to: a first antenna, having a first set of electromagnetic field lobes and configured to pass a first signal; a second antenna, having a second set of electromagnetic field lobes and configured to pass a second signal; wherein the modulation unit is configured to vary the first signal and the second signal, resulting in a third set of electromagnetic field lobes from a combination of the first and second sets of electromagnetic field lobes; wherein the first, second and third electromagnetic field lobes are in a same plane; and wherein a number of the third set of lobes is less than or equal to either a number of the first set of lobes or a number of the second set of lobes.

Abstract: A method includes receiving a first progress request from a first state machine associated with execution of a first thread on a processor. The method includes updating a current state of a temporal relationship state machine based on the current state, the first progress request, and a predetermined temporal relationship between progress of the first state machine to a first state machine state and progress to a second state. The predetermined temporal relationship may require the first state machine to progress to the first state machine state before the progress to the second state. The current state of the temporal relationship state machine may be one of a first temporal relationship state and a second temporal relationship state. The second state may be a second state machine state of the first state machine. The second state may be a second state machine state of a second state machine.

Abstract: A low voltage differential signaling circuit includes an output driver circuit configured to provide a differential signal pair based on a first signal and a second signal. A peak detect circuit is coupled to receive the differential signal pair and configured to provide a feedback signal based on the differential signal pair and the first and second signals. An amplifier circuit has a first input coupled to the peak detect circuit, a second input coupled to receive a reference voltage, and an output coupled to provide a bias voltage to the output driver circuit.

Abstract: A voltage regulator circuit that regulates voltage on an output node that provides power to a load circuit having varying current draw. A feedback voltage from the output node is compared to reference voltages. In response to the comparisons, pull-up/down circuits are applied to a gate-control node connected to the gate of a pass transistor. The voltage of the gate-control node is adjusted by integrating current from the pull-up/down circuits. In response to the feedback voltage being between the first and second reference voltages, the voltage on the gate-control node is maintained by disabling the pull-up/down circuits at the gate-control node.

Abstract: A device and a method for executing a program, and a method for storing a program are described. The method of executing a program includes a sequence of instruction cycles, wherein each instruction cycle comprises: updating the program counter value; reading a data word from a memory location identified by the updated program counter value, wherein the data word comprises an instruction and a protection signature; determining a verification signature by applying a signature function associated with the program counter value to the instruction; executing the instruction if the verification signature and the protection signature are consistent with each other; and initiating an error action if they are inconsistent with each other. A method for storing a program on a data carrier is also described.

Abstract: Microelectronic packages having hermetic cavities are provided, as are methods for producing such packages. In one embodiment, the microelectronic package includes a sensor die having first and second Microelectromechanical Systems (MEMS) transducer structures formed thereon. First and second cap pieces are coupled to the sensor die by, for example, direct or indirect bonding. A first hermetic cavity encloses the first MEMS transducer structure and is at least partially defined by the first cap piece and the sensor die. Similarly, a second hermetic cavity encloses the second MEMS transducer structure and at least partially defined by the second cap piece and the sensor die. A vent hole is fluidly coupled to the first hermetic cavity and is sealed by the second cap piece.

Abstract: Systems and methods for operating a DMA unit with address alignment are disclosed. These may include configuring a bandwidth control setting for a read job that includes a data transfer size corresponding to a first number of bytes. A second number of bytes to reach a read address alignment is determined. In a first data transfer, a third number of bytes substantially equal to the first number of bytes plus the second number of bytes are transferred. In subsequent data transfers of the read job, the first number of bytes are transferred to the data buffer. After the third number of bytes are transferred to the data buffer, a fourth number of bytes from the data buffer are transferred to a destination.

Abstract: A packaged integrated circuit (IC) device includes a first IC die with a first inductor, a first layer of adhesive on a first major surface of the first IC die, an isolation layer over the first layer of adhesive, a second layer of adhesive on the isolation layer, a second IC die on the second layer of adhesive, and a second inductor in the second IC die aligned to communicate with the first inductor. The isolation layer extends a prespecified distance beyond a first edge of the second IC die.

Abstract: A level shifter circuit to translate a first voltage level and a second voltage level of a signal is disclosed. The level shifter circuit includes a comparator. The comparator includes an input differential transistor pair with a matched current mirror load. The level shifter also includes a parallel signal path circuit to reduce the voltage transition lag caused by the comparator, a hysteresis adjusting device and a reference voltage generator circuit to provide a reference voltage to the comparator.

Abstract: In a data processing system, a store request is provided having corresponding store data and a corresponding access address, and a memory coherency required attribute corresponding to the access address of the store request is provided. When the store request results in a write-through store due to a cache hit or results in a cache miss, the corresponding access address and store data is stored in a selected entry of the store buffer and a merge allowed indicator is stored in the selected entry which indicates whether or not the selected entry is a candidate for merging. The merge allowed indicator is determined based on the memory coherency required attribute from the MMU and a store buffer coherency enable control bit of the cache. Entries of the store buffer which include an asserted merge allowed indicator and share a memory line in the memory are merged.

Abstract: The disclosure relates to an IQ mismatch correction module for a radio receiver, the IQ mismatch correction module comprising: an input terminal configured to receive an input signal; an output terminal configured to provide a filtered output signal; a mismatch detection module comprising: one or more bandpass filters configured to receive, from the input terminal or output terminal, a bandpass input signal and to pass a plurality of sub-bands of the bandpass input signal to provide respective bandpass filtered signals; one or more amplitude and phase mismatch detectors configured to determine amplitude and phase mismatch coefficients based on the bandpass filtered signals from the plurality of sub-bands; a transformation unit configured to apply a transformation to the amplitude and phase mismatch coefficients to provide correction filter coefficients for the plurality of sub-bands; and a filter module configured to: receive the filter coefficients for the plurality of sub-bands from the mismatch detection m

Abstract: A method of protecting a dielectric during fabrication is provided. A conductive layer is patterned to form a first conductive shape on a first portion of a dielectric layer and a second conductive shape on a second portion of the dielectric layer. A conductive trace is formed over at least a portion of the second conductive shape. The conductive trace electrically connects the first conductive shape with a substrate tie. An interconnect layer is coupled to the first conductive shape. The conductive trace is etched to electrically isolate the first conductive shape from the substrate tie.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes three or more bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and a diode connected in series with the three or more bipolar transistors and one of the first and second nodes. Each of the three or more bipolar transistors includes a collector comprising collector components, an emitter comprising emitter components, and a base structure comprising a substrate region or an active region. The emitter components are alternately located with respect to the collector components. The substrate region or the active region surrounds the collector components and the emitter components. Other embodiments are also described.

Abstract: A power control system, method, and architecture are disclosed for a multi-bank memory which provides independent, concurrent memory access to at least one memory block in each memory bank by using observation circuits to monitor bus masters connected over bus master interface signals to an interconnect for memory access requests to the multi-bank memory and to provide notifications to a power control circuitry that a valid memory access request was issued by a bus master over the bus master interface, where the power control circuitry processes the notifications received from each observation circuit and generates therefrom power control signals that are provided directly to each memory block and to bypass the interconnect, thereby separately controlling a power state for each memory block with power-up control signals that arrive at each memory block at or before a memory access request sent over the interconnect.

Abstract: In accordance with a first aspect of the present disclosure, a near field communication (NFC) controller is provided, comprising a load modulation amplitude control unit configured to control a load modulation amplitude of one or more signals transmitted through an NFC antenna, wherein said load modulation amplitude control unit is further configured to change said load modulation amplitude in dependence on a supply voltage. In accordance with a second aspect of the present disclosure, a corresponding method of operating a near field communication (NFC) controller is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.

Abstract: High thermal performance microelectronic modules containing thermal extension levels are provided, as are methods for fabricating such microelectronic modules. In various embodiments, the microelectronic module includes a module substrate having a substrate frontside and a substrate backside. At least one a microelectronic device, such as a semiconductor die bearing radio frequency circuitry, is mounted to the substrate frontside. A substrate-embedded heat spreader, which is thermally coupled to the microelectronic device, is at least partially contained within the module substrate, and extends to the substrate backside. A thermal extension level is located adjacent the substrate backside and extends away from the substrate backside to terminate at a module mount plane. The thermal extension level contains a heat spreader extension, which is bonded to and in thermal communication with the substrate-embedded heat spreader.

Abstract: A low frequency (LF) antenna control circuit is disclosed. The LF antenna control circuit includes an antenna driver to drive an antenna, a current and phase measurement circuit to measure antenna current and signal phase, a modulator to modulate a signal to be transmitted via the antenna and a controller configured to drive the antenna through the antenna driver using a first fixed amplitude for a first time period, a second fixed amplitude for a second time period that is subsequent to the first time period and subsequent to the second time period, and subsequently, to drive the antenna using step up/down voltages based on the measured antenna current and signal phase. The signal included encoded bits of data to be transmitted.

Abstract: A device comprising includes an output terminal and a first current path from the output terminal to a first reference voltage. The first current path includes a series connection of current electrodes of a first transistor and a second transistor. The first transistor receives at a control electrode a signal to set a desired level of current to be conducted by the first current path. The second transistor generates at a control electrode a feedback signal indicative of an actual current conducted by the first transistor.

Abstract: The present application relates to a circuit of a frequency divider arranged to divide a frequency of an input clock signal by odd integer N and a method of operating the circuit. A shift register comprises a number of N+1 clock gating cells, which are connected in series to each other, and a shift logic. An input clock signal is fed into clock signal inputs of each one of the number of N+1 clock gating cells. The shift logic is configured to receive enable signals from a set of the number of N+1 clock gating cells and to generate a feedback signal, which is supplied to a gate enable input of the first one of the number of N+1 clock gating cells. A multiplexer is configured to receive at input ports N+1 gated clock signals and to output a rotation clock signal, which has a frequency of 2/N of the frequency of the input clock signal. A frequency generator is configured to receive the rotation clock signal and to generate an output clock signal having a frequency of 1/N.

Abstract: A function monitor for a system, such as an advanced driver assistance system, comprising a first function monitor element and a second function monitor element, said first function monitor element configured to receive and collate sensor data from a plurality of sensors associated with the system and send a function warning signal to said second function monitor element when said sensor data from one or more of the plurality of sensors is indicative of a functional irregularity.