Abstract: Embodiments for a level shifter are provided, including: a current mirror comprising a reference current transistor and a mirrored current transistor; a pull-down network comprising a first and a second pull-down transistor, wherein the first and second pull-down transistors are respectively connected in series with the reference and mirrored current transistors; a pull-up transistor connected to an intermediate node located between the mirrored current transistor and the second pull-down transistor; a transition control transistor connected to the gate electrode of the reference current transistor; a cut-off transistor connected between the first pull-down transistor and a common negative power supply voltage; and a first and a second inverter connected to the intermediate node, wherein a control node is located between the first and second inverters, and gate electrodes of the pull-up transistor, the transition control transistor, and the cut-off transistor are connected to the control node.

Abstract: A set of initialization parameters are generated for a wireless charging device. Parameters of an antenna circuit connected to an output of the control circuit are measured. The antenna circuit is modelled as first and second virtual antenna portions. The presence of a foreign object is detected by receiving, from a receiver device, characteristics for the antenna circuit and by measuring second parameters of the antenna circuit. The measured second parameters and the initialization parameters are used to determine characteristics for the first virtual antenna portion. A foreign object is detected based upon a comparison of the received characteristics for the antenna circuit and the determined characteristics for the first virtual antenna portion.

Abstract: An embodiment for bandgap reference voltage circuitry includes: a bandgap reference voltage generator including: a first bipolar junction transistor (BJT); a first amplifier having a non-inverting input coupled to a collector of the first BJT and a first output node configured to provide a bandgap reference voltage; a first resistor coupled between a base of the first BJT and the first output node; a second BJT; a second amplifier having a non-inverting input coupled to a collector of the second BJT and a second output node coupled to a junction node; a second resistor coupled between a base of the second BJT and the junction node; and a third resistor coupled between the base of the first BJT and the junction node.

Abstract: Embodiments of an electrostatic discharge (ESD) protection device and a method for operating an ESD protection device are described. In one embodiment, an ESD protection device includes stacked first and second PNP bipolar transistors that are configured to shunt current between a first node and a second node in response to an ESD pulse received between the first and second nodes and an NMOS transistor connected in series with the stacked first and second PNP bipolar transistors and the second node. An emitter and a base of the second PNP bipolar transistor are connected to a collector of the first PNP bipolar transistor. A gate terminal of the NMOS transistor is connected to a source terminal of the NMOS transistor. Other embodiments are also described.

Abstract: An electronic circuit, including an equalizer circuit to input a differential signal, a rectifier circuit to receive the differential signal and output a first current and a second current, a replica circuit to receive a differential threshold signal and output a third current and a fourth current to compensate for PVT variations in the first and second currents, and a comparator circuit configured to compare a differential voltage generated based on the first, second, third, and fourth currents to determine a loss of signal event of the electronic circuit.

Abstract: An inertial sensor includes a proof mass spaced apart from a surface of a substrate. The proof mass has a first section and a second section, where the first section has a first mass that is greater than a second mass of the second section. An anchor is coupled to the surface of the substrate and a spring system is interconnected between the anchor and the first and second sections of the proof mass. The spring system enables translational motion of the first and second sections of the proof mass in response to linear acceleration forces imposed on the inertial sensor in any of three orthogonal directions.

Abstract: A cap wafer bonded to a device wafer by a metal polysilicon germanium material to form a sealed chamber around a semiconductor device is provided. On the cap wafer, a stack of silicon (Si), polycrystalline silicon germanium (SiGe), and polycrystalline germanium (Ge) is formed. This stack of material layers is formed to intentionally have a roughened germanium surface. A metal structure is formed on a second wafer, having an anti-stiction coating layer on the surface of the metal structure. A metal silicon germanium bonding material is formed by placing the metal structure and germanium structure in contact and applying heat and pressure. The roughened germanium layer penetrates the anti-stiction coating layer upon application of the pressure. The germanium that penetrates to the metal is free of interfacial anti-stiction coating and allows for eutectic bond formation upon application of heat.

Abstract: A system includes a first unit associated with an object and a second unit. The first unit includes a first transceiver coupled with first processing circuitry. The second unit includes a second transceiver coupled with second processing circuitry. Methodology includes establishing a bidirectional wireless communication link between the first and second units. Following establishment of the communication link, the first and second units exchange messages. The first processing circuitry measures a first received signal strength indicator (RSSI) value for each of the messages received at the first unit and sends the first RSSI value in a subsequent message to the second unit. The second processing circuitry measures a second RSSI value for each of the messages received at the second unit and sends the second RSSI value in another subsequent message to the first unit. A relay attack is determined in response to the first and second RSSI values.

Abstract: A resonant converter circuit comprising a controller having a Vbusdiv-input-terminal configured to receive a Vbusdiv-input-signal; and a Vbus-compensation-network. The Vbus-compensation-network comprising: a Vbus-input-terminal configured to receive a bus-voltage-signal; and a Vbusdiv-output-terminal configured to provide the Vbusdiv-input-signal to the controller; a reference terminal; an AC-impedance-network connected between the Vbus-input-terminal and the Vbusdiv-output-terminal, wherein the AC-impedance-network is configured to apply an AC transfer function to the received bus voltage signal; a DC-impedance-network connected between the Vbus-input-terminal and the Vbusdiv-output-terminal, wherein the DC-impedance-network is configured to apply a DC transfer function to the received bus voltage signal. The DC transfer function is different to the AC transfer function. The controller is configured to control operation of a resonant converter in accordance with the Vbusdiv-input-signal.

Abstract: Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a Controller Area Network (CAN) transceiver involves detecting phase information related to a CAN data frame that is transmitted by the CAN transceiver and in response to the phase information, switching between different transmitter configurations of the CAN transceiver within a bit interval for use in transmitting subsequent bits of the CAN data frame.

Abstract: The present invention relates to a bandwidth estimation circuit for estimating and predicting the bandwidth of a computer system, the bandwidth estimation circuit comprising: a memory unit which is configured to store multiple predetermined bandwidth envelopes, wherein each one of the predetermined bandwidth envelopes is assigned to a feature of a code of an application program; a bandwidth measurement unit which is configured to online measure the bandwidth of a data transaction based on the code; a selection unit coupled either to the memory unit and the bandwidth measurement unit and configured to find the nearest bandwidth envelopes in the memory unit for the measured bandwidth; a calculation unit which is configured to calculate a ratio between the selected bandwidth envelopes, to construct a new bandwidth envelope by applying an interpolation function based on the calculated ratio and to calculate an estimated bandwidth by applying the new bandwidth envelope.

Abstract: A method includes fabricating a set of die in a production run, each die comprising a set of pads at a periphery of a top metal layer, a first set of fuse elements, and a second set of fuse elements. Each fuse element of the first set of fuse elements couples a corresponding pad of the set to a corresponding bus when in a conductive state, and each fuse element of the second set couples a corresponding subset of pads of the set together when in a conductive state. The method further includes selecting a subset of the die of the production run for testing, and configuring each die of the subset for testing by placing each fuse element of the first set in a non-conductive state and placing each fuse element of the second set in a conductive state.

Abstract: A transistor includes a trench formed in a semiconductor substrate with the trench having a first sidewall and a second sidewall. A vertical field plate is formed in the trench. The vertical field plate is located between the first sidewall and the second sidewall. A gate electrode is formed in the trench with a first edge of the gate electrode proximate to the first sidewall and a second edge of the gate electrode proximate to the vertical field plate. A dielectric material is formed in the trench between the first sidewall and the vertical field plate. An air cavity is formed in the trench between the vertical field plate and the second sidewall with the air cavity having a dielectric constant lower than that of the dielectric material.

Abstract: A method embodiment includes combining a control signal of a voltage regulator circuit of an apparatus with pseudo-random noise, and using the control signal to provide an output voltage signal as attenuated by a power supply rejection ratio (PSRR) of an analog mixed-signal (AMS) circuit of the apparatus. The method further includes self-testing the AMS circuit by cross-correlating a signal indicative of the output voltage signal from the AMS circuit with the pseudo-random noise and, in response, assessing the results of the cross-correlation relative to a known threshold indicative of a performance level of the AMS circuit.

Abstract: A scan circuit and methods of operating a scan circuit are provided. The method for operating a scan circuit includes providing a first scan flip-flop which includes an overwrite feature. With the overwrite feature enabled, a change in functional behavior of the first scan flip-flop occurs based on a control signal. The method may further include capturing data at a first input of the first scan flip-flop during a first state of the control signal and resetting captured data by using the overwrite feature during a first transition of the control signal. The method may further include forming a scan chain with one or more of the first scan flip-flops and one or more second scan flip-flops. The second scan flip-flops may include a similar overwrite feature, having the overwrite feature disabled.

Abstract: Embodiments of a buffer device, an electronic system, and a method for operating a buffer device are disclosed. In an embodiment, a buffer device includes buffer bus connections, a peripheral bus interface connectable to a peripheral bus, a buffer memory module, and a buffer memory controller connected between the buffer bus connections, the peripheral bus interface, and the buffer memory module. Each of the buffer bus connections is connectable to a respective peripheral device. The buffer memory module comprises memory segments corresponding to the peripheral devices. The buffer memory controller is configured to control data communications between the buffer bus connections, the peripheral bus interface, and the buffer memory module.

Abstract: A circuit for detecting charger connection through a universal serial bus (UBS) connector is disclosed. The circuit includes a comparator having a first input coupled to a fixed voltage reference and a second input coupled to D+ pin of the USB connector, a voltage controlled current source (VCCS) coupled having a first terminal coupled to a supply and a second terminal coupled to the D+ pin and a resistor coupled between the first terminal and the second terminal of the VCCS. The VCCS is configured to bring voltage at the D+ pin within a preselected voltage range at the D+ pin when the voltage at the D+ pin varies beyond the preselected voltage range.

Abstract: An amplifier includes a differential input stage, a hysteresis stage, coupled to the differential input stage, a cascode stage coupled to the hysteresis stage, a feedback stage coupled to an output of the cascode stage and configured to provide a feedback signal to the hysteresis stage, and an output stage coupled to the output of the cascode stage. The output stage includes a hysteresis inverter coupled between the output of the cascode stage and the amplifier output.

Abstract: An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.

Abstract: According to a first aspect of the present disclosure, an electronic tamper detection device is provided, comprising a tamper loop and a deformable component, wherein a deformation of said component indicates that the tamper loop has been broken. According to a second aspect of the present disclosure, a corresponding method of producing a tamper detection device is conceived.