Abstract: A method is provided for generating a public/private key pair on an IC and to provision an IoT device having the IC. In the method, a first entity manufacturers an integrated circuit (IC) for use in a device. The IC, or chip, has a root secret embedded therein. A public key is generated on the IC using a unique identifier (ID) and the root secret. The IC is provided to a second entity for manufacturing the device using the IC. A reference IC is provided to a third entity. The reference IC has the same embedded root secret as the IC. The reference IC is configured to use the unique ID of the IC and the embedded root secret to generate a derived public key. The third entity is enabled to verify that the public key of the IC is associated with the unique ID by using the derived public key of the reference IC. The method allows the IoT device to be provisioned without using a public key infrastructure.

Abstract: A multi-bit continuous-time sigma-delta modulator, SDM, includes an input configured to receive an input analog signal; a first summing junction configured to subtract a feedback analog signal from the input analog signal; a loop filter configured to filter an output signal from the first summing junction: an analog-to-digital converter, ADC, configured to convert the filtered analog output signal to a digital output signal; and a feedback path for routing the digital output signal to the first summing junction. The feedback path includes a plurality of digital-to-analog converters, DACs, configured to convert the digital output signal to an analog form. The ADC includes multiple per-bit parallel loops, each loop configured to provide a per-bit current summation of the filtered analog output signal such that an output of the multiple per-bit parallel loops is a multi-bit quantization digital output signal.

Abstract: A chirp-generator comprising a phase-detector for providing a phase-difference-signal representative of a phase difference between a clock-input-signal and a feedback-signal. A VCO-circuit is configured to provide a chirp-generator-output-signal based on the phase-difference-signal. The VCO-circuit comprises a switched-varactor-bank, which includes a plurality of varactors, and a varactor-switch associated with each of the plurality of varactors. The varactor-switch is configured to selectively control whether or not the associated varactor contributes to the capacitance of the VCO-circuit, based on the state of a varactor-control-signal. The chirp-generator also includes a feedback-component configured to: receive the chirp-generator-output-signal; and apply a variable-multiplication-factor to the chirp-generator-output-signal in order to provide the feedback signal for the phase-detector.

Abstract: A motion-detection-circuit configured to receive an audio-output-signal and a received-motion-signal. The motion-detection-circuit includes a preliminary-motion-detector configured to process the received-motion-signal in order to set a state of a prelim-motion-detected-signal based on the received-motion-signal; and an ADC for providing an ADC-output-signal that is a digital representation of a signal received at an ADC-input-terminal. The motion-detection-circuit also includes a switch configured to connect either (i) an audio-output-receiver or (ii) a motion-signal-receiver-terminal to the ADC-input-terminal based on the state of the prelim-motion-detected-signal.

Abstract: The present application relates to a hysteresis comparator, which comprises a hysteresis comparator circuit and a hysteresis generating circuit. The hysteresis comparator circuit two comparator legs each with a differential transistor and a load transistor. The differential transistors receive a comparator biasing current, which is variably divided based on the relative levels of the voltage signals applied to control terminals of the differential transistors. An output stage is provided for developing an output voltage signal based on currents flowing through the load transistors. The hysteresis generating circuit is arranged for selectively injecting a hysteresis current in or selectively drawing a hysteresis current from either one of the two comparator legs depending on the level of the output voltage signal.

Abstract: A plurality of trench stripes are disposed in parallel in an epitaxial layer on a drain and extends from a top region to a bottom region of a first surface of the semiconductor. A first polysilicon layer is in each of the trench stripes. The first polysilicon layer extends between the drain and the first surface proximal to the top region and the bottom region, and between the drain and a level below the first surface in a middle region between the top region and the bottom region. A second polysilicon layer is over the first polysilicon layer in the middle region, wherein the first poly silicon layer forms a shield, and the second polysilicon layer forms a gate. A source is in a silicon mesa stripe surrounding the first trench stripe.

Abstract: A device includes multiple ceramic capacitors and a current path structure. A first ceramic capacitor includes a first ceramic material between first and second electrodes. A second ceramic capacitor includes a second ceramic material between third and fourth electrodes. The second ceramic material has a higher Q than the first ceramic material. The current path structure includes a lateral conductor located between the first and second ceramic materials, and first and second vertical conductors that extend from first and second ends of the lateral conductor to a device surface. The device may be coupled to a substrate of a packaged RF amplifier device, which also includes a transistor. For example, the device may form a portion of an output impedance matching circuit coupled between a current carrying terminal of the transistor and an output lead of the RF amplifier device.

Abstract: A semiconductor switch device and a method of making the same. The method includes providing a semiconductor substrate having a major surface and a first semiconductor region having a first conductivity type. The method further includes implanting ions into the first semiconductor region through an opening in a mask positioned over the first semiconductor region, thereby to form a well region located in the first semiconductor region, the well region having a second conductivity type different to the first conductivity type. The method also includes depositing and patterning a gate electrode material on a gate dielectric to form a gate electrode located directly above the well region. The method further includes performing ion implantation to form a source region located in the well region on a first side of the gate, and to form a drain region located outside the well region on a second side of the gate.

Abstract: A reference voltage circuit with current buffer including a low voltage reference to output a low voltage, a first resistor-capacitor (RC) filter to filter the low voltage, a buffer circuit to output a current to be used by a load, a second RC filter associated with the load, and a capacitor in parallel with the buffer circuit configured to increase a rise time of the buffer.

Abstract: A method of making a plurality of packaged semiconductor devices. The method includes providing a carrier blank having a die receiving surface and an underside. The method also includes mounting a plurality of semiconductor dies on the die receiving surface, wherein the dies extend to a first height above the die receiving surface. The method further includes depositing an encapsulant on the die receiving surface, wherein an upper surface of the encapsulant is located above said first height. The method also includes singulating to form the plurality of packaged semiconductor devices by sawing into the underside, through the carrier blank and partially through the encapsulant to a depth intermediate the first height and the upper surface, wherein said sawing separates the carrier blank into a plurality of carriers, and removing encapsulant from the upper surface of the encapsulant at least until said saw depth is reached.

Abstract: A decoder decodes a set of data streams received at a receiver based on a tree search that employs a subset of decoding constellation points. The decoder can form a tree wherein each level of the tree corresponds to one of the set of data streams. Each level of the tree includes a plurality of nodes corresponding to a set of candidate constellation points, wherein the set of candidate constellation points indicating possible values of data received via the set of data streams. For tree levels beyond an initial tree level, the decoder expands each node (that is, calculates the metrics for nodes of the next tree level) for only a subset of candidate constellation points, wherein the subset of candidate constellation points is based on a sign value of the node.

Abstract: A power management device includes a first switch to couple a first node corresponding to a first reference voltage to a first terminal of a first device component in response to receiving a first indicator at a first time, a compare circuit to determine at a second time that a voltage at the first terminal exceeds a first threshold value, and a second switch to couple a second node corresponding to a second reference voltage to the first terminal in response the determining.

Abstract: A method, system, and apparatus are provided for computing soft bits in a non-linear MIMO detector which decodes a signal received at a plurality of receive antennas using channel estimate information and a decoding tree to produce output data for a bit estimation value which includes a maximum likelihood solution along with a naturally ordered vector identifying all explored node metrics and node indices, where soft bits are computed for each bit estimation value by determining a set of bit-masks through repetition and indexing operations applied on the explored node indices, masking the naturally ordered vector with the set of bit-masks to generate masked node metrics, determining candidate soft bit values by subtracting metrics of all nodes that form the maximum likelihood solution from the masked node metrics, and determining a final soft bit value by identifying which of the candidate soft bit values has a lowest value.

Abstract: A circuit for a switched-mode-power-supply. The switched-mode-power-supply is configured to: receive a current-control-signal; and provide an output-voltage based on the current-control-signal. The circuit comprises a controller, a current-limiter and a clamp-circuit. The controller is configured to: generate a control-voltage based on the difference between: (i) a sense-voltage, which is representative of the output-voltage of the switched-mode-power-supply; and (ii) a reference-voltage; generate a target-current-control-signal based on the control-voltage, wherein the target-current-control-signal is configured to adjust the current through the switched-mode-power-supply in order to bring the sense-voltage closer to the reference-voltage. The current-limiter is configured to provide the current-control-signal as the target-current-control-signal limited to a max-current-control-value.

Abstract: A memory system comprising: a memory cell. The memory cell comprising a poly-fuse-resistor; and a bipolar junction transistor having a collector-emitter channel and a base-terminal. The collector-emitter channel of the bipolar junction transistor is connected in series with the poly-fuse resistor between a supply-voltage-terminal and a ground-terminal. The base-terminal of the bipolar junction transistor is configured to receive a transistor-control-signal to selectively control a current flow through the poly-fuse-resistor.

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

Abstract: Embodiments are provided that include a method for fabricating a multi-die package including: placing a plurality of flip chip dies and splitter dies on the sacrificial carrier; performing solder reflow to join solder bumps of each flip chip die and each splitter die to the sacrificial carrier that includes test probe circuitry; testing the flip chip and splitter dies; replacing any faulty dies; overmolding the flip chip and splitter dies on the sacrificial carrier to form a panel of embedded dies; planarizing the panel of embedded dies to expose back surfaces of the embedded dies; forming a metallization layer across the back surface of the panel of embedded dies; and removing the sacrificial carrier to expose a front surface of the panel of embedded dies, wherein a contact surface of each solder bump of each flip chip die and splitter die is exposed in the front surface.

Abstract: An embodiment for bandgap reference voltage circuitry includes: a bandgap reference voltage generator including: a first bipolar junction transistor (BJT); a first amplifier having a non-inverting input coupled to a collector of the first BJT and a first output node configured to provide a bandgap reference voltage; a first resistor coupled between a base of the first BJT and the first output node; a second BJT; a second amplifier having a non-inverting input coupled to a collector of the second BJT and a second output node coupled to a junction node; a second resistor coupled between a base of the second BJT and the junction node; and a third resistor coupled between the base of the first BJT and the junction node.

Abstract: Microelectronic systems having embedded heat dissipation structures are disclosed, as are methods for fabricating such microelectronic systems. In various embodiments, the method includes the steps or processes of obtaining a substrate having a tunnel formed therethrough, attaching a microelectronic component to a frontside of the substrate at a location covering the tunnel, and producing an embedded heat dissipation structure at least partially within the tunnel after attaching the microelectronic component to the substrate. The step of producing may include application of a bond layer precursor material into the tunnel and onto the microelectronic component from a backside of the substrate. The bond layer precursor material may then be subjected to sintering process or otherwise cured to form a thermally-conductive component bond layer in contact with the microelectronic component.

Abstract: Aspects are directed to a wireless communications approach in which a signal is conveyed via one of a number of particular frequency bands. In one example, a tank circuit includes an inductor and multiple capacitive circuits, and a driver circuit includes multiple buffers. One of the buffers is responsive to the input signal and another of the buffers is not responsive to the input signal. The driver circuit is configured to drive the tank circuit through a respective capacitive circuit while coupled to a respective buffer at a node of the inductor. A tuning-drive circuit drives the tank circuit for communicating in one band of a selectably-tunable frequency range. The tuning-drive circuit includes selectable (buffer and capacitor) portions configured to selectively couple to the node, for an overall drive strength and an overall tuning capacitance, and for tuning the tank circuit to a selected frequency band for wireless communication.