Abstract: A circuit includes a first amplifier path configured to carry a first radio frequency signal, a second amplifier path configured to carry a second radio frequency signal, a first resonator connected to the first and second amplifier paths, the first resonator being configured to resonate at a radio frequency to isolate the first and second radio frequency signals from one another and further configured to pass signals at a baseband frequency, and a second resonator coupling the first resonator and a reference voltage node, the second resonator being configured to pass signals at the baseband frequency to the reference voltage node.

Abstract: A device includes a semiconductor substrate, a doped isolation barrier disposed in the semiconductor substrate, a body region disposed in the semiconductor substrate within the doped isolation barrier and in which a channel is formed during operation, an isolation contact disposed at the semiconductor substrate and to which a voltage is applied during operation, and a plurality of reduced surface field (RESURF) layers disposed in the semiconductor substrate, the plurality of reduced surface field (RESURF) layers being arranged in a stack between the body region and the isolation contact.

Abstract: Aspects of the present disclosure are directed to methods and apparatuses involving a chip carrier having openings therein that align integrated circuit (IC) chips relative to an alignment feature. The IC chips and carrier are tested, such as by final testing the affixed IC chips after manufacture, and further testing after subjecting the affixed IC chips to one or more stress conditions. A test probe is aligned to one or more contacts on each chip based on the location of an alignment feature of the carrier relative to the opening in which the IC chip being tested is located. Responsiveness of the IC chip, before and after application of the one or more stress conditions, can be assessed by probing the IC chip via the aligned test probe, and assessing electrical signals received over the test probe.

Abstract: The dies of a stacked die IC are tested and, in response to detection of a defect at one of the dies, the type of defect is identified. If the defect is identified as a defective module repairable at the die itself, a redundant module of the die is used to replace the functionality of the defective module. If the defect is identified as one that is not repairable, a replacement die in the die stack is used to replace the functionality of the defective die.

Abstract: There is provided a network interface module, and a method of implementing deterministic response frame transmission therein. The network interface module comprises a processor core arranged to execute a set of threads, the set of threads comprising at least one transmit thread arranged to cause a response frame to be transmitted upon expiry of a minimum response period from a response triggering event occurring. The network interface module further comprises a timing component arranged to output a masking timeout signal indicating expiration of successive masking timeout intervals, and a masking component arranged to mask the transmit thread from being scheduled for execution by the processing core. The masking component being further arranged to receive the masking timeout signal output by the timing component and to unmask the transmit thread upon expiry of a masking timeout interval.

Abstract: A method including performing a delay measurement of a first round trip delay value of an interface link, the first round trip delay value based on a transmission of a first REC synchronization signal to a RE and when a REC receives a first RE synchronization signal back, wherein frames transmitted by the REC are synchronized based upon the first REC synchronization signal, and frames transmitted by the RE are synchronized based upon the first RE synchronization signal. Calculating a first delay change value between the first round trip delay value and a previous round trip delay value, in response to determining that the first delay change value violates a delay tolerance value, transmitting an offset indicator that indicates an amount of offset the RE is to shift the first RE synchronization signal at a future time, and transmitting frames from the REC after shifting the first REC synchronization signal.

Abstract: An overcharge protection circuit comprises a first series of first terminals a second series of second terminals, a first overvoltage protection device connected between each consecutive pair of first terminals, a current balancing device connected between each consecutive pair of second terminals, and a second overvoltage protection device connected between a first terminal and a second terminal. The second overvoltage protection device is configured to pass a current if a voltage over the second overvoltage protection device exceeds a threshold. The second overvoltage protection device may comprise a bidirectional ESD diode, while both the first overvoltage protection device and the second overvoltage protection device may comprise a unidirectional ESD diode.

Abstract: Described herein is an N type extended drain transistor formed from a semiconductor on insulator (SOI) wafer. The transistor has a buried P type region formed by the selective implantation of P type dopants in a semiconductor layer of the wafer at a location directly below a drift region of the transistor. The transistor also includes a source located in a P well region and a drain. The buried P type region is in electrical contact with the P well region. The N type drift region, the source, and the drain are also located in a portion of the semiconductor layer surrounded by dielectric isolation. A buried dielectric layer located below the portion of the semiconductor layer electrically isolates the portion of the semiconductor layer from a semiconductor substrate located below the buried dielectric layer.

Abstract: Consistent with example embodiments, a wafer substrate undergoes processing in which a resilient material is applied to the front-side and back-side surfaces of the wafer substrate. By defining trenches in saw lanes between active device die, additional resilient material may be placed therein. In an example embodiment, after the active device die are separated into individual product devices, the resulting product device has coverage on the front-side surface, back-side surface, and the four vertical faces of the encapsulated active device die. The front-side surface has exposed contact areas so that the product device may be attached to an end user's system circuit board. Further, the resilient coating protects the encapsulated active device die from damage during assembly.

Abstract: Embodiments of an interface system for interfacing between an NFC controller and a secure element are disclosed. In one embodiment, an interface system includes an interface memory, an interface controller, an NFC controller interface configured to exchange data between the interface system and an NFC controller, and a secure element interface configured to exchange data between the interface system and a secure element.

Abstract: A method, system, and apparatus are provided for preventing glitch attacks by using a glitch processing hardware unit (1) to deactivate a glitch filter connected between the monitored line and a reset processing unit in response to detecting a voltage glitch on a monitored line during a specified security system sequence and (2) to automatically drive a requested reaction in response to the voltage glitch by driving one of a plurality of configurable reactions comprising a device reset reaction and a process restart request, thereby preventing the voltage glitch from maliciously influencing the specified security system sequence.

Abstract: A method for a method for mapping an input message to an output message by a keyed cryptographic operation in a cryptographic system, including a plurality of rounds wherein each round has a substitution layer, wherein wide encoding is used on the substitution layer in the rounds that require protection from attacks.

Abstract: A wireless receiver for a distributed antenna diversity receiver apparatus comprising a pre-combining component arranged to receive an RF signal from an antenna and to recover and output an information signal contained within the received RF signal, and a combined-signal component arranged to receive the recovered information signal output by the pre-combining component of the wireless receiver and a further recovered information signal from a further wireless receiver and to perform diversity combining of the recovered information signals to obtain and output an enhanced information signal. The wireless receiver further comprises a monitoring component arranged to receive intra-packet channel reliability parameters for the wireless receiver and for the further wireless receiver, determine whether to assign a new master receiver for the distributed antenna diversity receiver apparatus based on the received intra-packet reliability parameters.

Abstract: Embodiments utilizing secret keys for authentication and/or encrypted communication are described. In certain embodiments, authentication data is provided from a source network communication device to a target network communication device that allows a computing server to verify that the key migration is authorized by the source network communication device. The authentication data also enables the data provider and the target network communication device to independently determine a temporary key for establishing a secure communication channel between the service provider and the target network communication device and/or determine a new key for the target network communication device. In some implementations, the authentication data may be exchanged between the source and target network communication devices between offline without involvement of the computing server.

Abstract: A signal processing device includes at least one timestamp generation component arranged to generate at least one local timestamp value, and to provide the at least one local timestamp value to at least one data link layer module for timestamping of data packets. The signal processing device further includes at least one debug module arranged to receive the at least one local timestamp value and to timestamp debug information based at least partly on the at least one local timestamp value.

Abstract: A current clamp circuit includes a current-source circuit, a current-sense circuit, and a feedback circuit. The current-sense circuit includes a transistor, a resistive network, and a multiplexer. The transistor outputs a sensed current signal having a current that is equal to a current of an output signal provided by the current-source circuit. The feedback circuit limits the current of the sensed current signal and the output signal below a threshold current. The multiplexer modifies a resistance of the resistive network based on a first control signal. The multiplexer circuit and the feedback circuit are programmed using the first control signal and a second control signal when the transistor operates in a linear region and in a saturation region, respectively, to accurately output the sensed current signal.

Abstract: Various exemplary embodiments relate to an integrated circuit device that includes a plurality of input/output pins, device circuitry, a first testing protocol interface connected to the device circuitry and to the plurality of input/output pins, and a second testing protocol interface connected to the device circuitry and to the same plurality of input/output pins as the first testing protocol interface. The first testing protocol interface is configured to test the device circuitry with a first testing protocol, and the second testing protocol interface is configured to test the device circuitry with a second testing protocol.

Abstract: A near field communication (NFC) or Radio Frequency Identification (RFID) reader device for contact-less communication includes a transmitter block connected to an antenna via a matching circuitry. An electromagnetic carrier signal and modulated data information are emitted via this main antenna. Any secondary object brought into the vicinity of the main antenna influences the primary resonant circuit resulting in a load change seen by the transmitter. This detuning can cause increased power consumption, RF (Radio Frequency) standard incompliance, and device damage. The present disclosure describes devices and methods on how to detect detuning and how to regulate the transmitter's output.

Abstract: A receiver circuit comprising: an input terminal configured to receive an input-signal; a feedforward-ADC configured to provide a feedforward-digital-signal based on the input-signal; a feedforward-DAC configured to provide a feedforward-analog-signal based on the feedforward-digital-signal; a feedforward-subtractor configured to provide an error-signal based on the difference between the feedforward-analog-signal and the input-signal; an error-LNA configured to provide an amplified-error-signal based on the error-signal; an error-ADC configured to provide a digital-amplified-error-signal based on the amplified-error-signal; a mixer configured to down-convert a signal in a signal path between the input terminal and the error-ADC; and an error-cancellation-block configured to provide an error-cancelled-signal based on a difference between the digital-amplified-error-signal and the feedforward-digital-signal.

Abstract: A packaged semiconductor structure includes an interconnect layer and a first microelectronic device on a first major surface of the interconnect layer. The structure also includes a substrate having a cavity, wherein the cavity is defined by a vertical portion and a horizontal portion, wherein the vertical portion surrounds the first device, the horizontal portion is over the first device, and the first device is between the horizontal portion and the first major surface of the interconnect layer such that the first device is in the cavity. The structure further includes a second microelectronic device attached to the horizontal portion of the substrate, and encapsulant on the interconnect layer and surrounding the first device, the substrate, and the second device, such that the substrate is embedded in the encapsulant.