Abstract: A data processing device for executing a program is described. The program comprises one or more instruction groups and one or more predicates, each instruction group comprising one or more instructions. The data processing device comprises a processing unit and a trace unit connected to or integrated in the processing unit. The trace unit generates a predicate trace for tracing the values of the one or more predicates. The processing unit executes, in each of a series of execution periods, one of the instruction groups and updated the values of none, one, or more of the predicates in dependence on the respective instruction group. The trace unit appends the updated values of the none, one, or more predicates to the predicate trace and does not append any non-updated values of the predicates. A method of reporting predicate values and a data carrier are also disclosed.

Abstract: An apparatus for installation within a tire for a vehicle includes a flexible arm and a power generating element coupled to the flexible arm for generating electrical energy. One end of the flexible arm is coupled to a rim of the tire. The opposing end of the flexible arm is configured to be in contact with the inside tread surface of the tire. The flexible arm is capable of deformation in response to a variability of distance between the rim and the inside tread surface during rolling movement of the tire, and the power generating element generates the electrical energy in response to deformation of the flexible arm. The apparatus may be combined with a tire pressure sensor module as a system so as to provide electrical energy for powering the tire pressure sensor module.

Abstract: A sensor for sensing an external magnetic field along a sensing direction comprises a sensor bridge. The sensor bridge has a first sensor leg that includes a first magnetoresistive sense element and a second sensor leg that includes a second magnetoresistive sense element. The first and second sense elements have respective first and second pinned layers having the same reference magnetization. The first and second sense elements have respective first and second sense layers, each self-biased to have a first sense magnetization. A permanent magnet layer is proximate the second sense element. In the absence of an external magnetic field, the permanent magnet layer magnetically biases the first sense magnetization of the second sense layer produce a second sense magnetization of the second sense layer that differs from the first sense magnetization, and the first sense layer of the first sense element retains the first sense magnetization.

Abstract: Embodiments of a microelectronic packaged device and methods of making are provided, where the microelectronic packaged device includes a system package comprising a first die and a second die, wherein the first die and the second die are laterally positioned to one another, and the first die and the second die are laterally separated from one another by mold compound; and a conductive trace formed between a first conductive surface on an exposed surface of the first die and a second conductive surface on an exposed surface of the second die, wherein the conductive trace is laser sintered directly on the first conductive surface, on a portion of the exposed surface of the first die, on a portion of a top surface of the mold compound, on a portion of the exposed surface of the second die, and on the second conductive surface.

Abstract: A memory device includes a non-volatile memory (NVM) array and a memory controller. The NVM array has four partitions in which each partition has as plurality of groups of NVM cells. The memory controller that performs a written operation on each of the four partitions in four cycles per group of NVM cells beginning a clock cycle apart in which two of the four clock cycles for the write operation are for an array write that requires a relatively high current and that the array write for each partition overlaps no more than one other array write so that a peak current of all four write operations is no more than twice the peak current of one group. The NVM cells may be magnetic tunnel junctions (MTJs) which have significantly faster written times than typical NVM cells.

Abstract: A processor device processes data samples of a radio signal in a mobile communication system. A fast flow process is executed for all samples and a batch process is executed at intervals on a subset of the samples. The device has a processor for executing the flow process via a local buffer memory, a memory interface to a system memory, and a memory controller for controlling storing of the data samples in the buffer memory. The processor establishes whether data samples in the local buffer memory are part of the subset, and if not, invalidates them after executing the flow process. The memory controller provides free memory space in the local buffer by transferring data samples which are not invalidated from the local buffer memory to the system memory, and by invalidating processed samples. Advantageously the local buffer may be relatively small, while the amount of data transferred to the system memory is limited.

Abstract: The present invention provides for a method and system for compensating phase offset caused by a matching network and antenna of a communications device. The method comprises: generating a mapping that correlates phase offset with a characteristic parameter; measuring the characteristic parameter for the communications device; using the measured characteristic parameter and the mapping to determine a phase offset for the communications device; and using the determined phase offset to compensate for the phase offset caused by the matching network and antenna of the communications device. The present invention also provides for a method and system for measuring a phase offset caused by a matching network and antenna of a communications device.

Abstract: Embodiments provided herein include a method for a clock gating verification during a register transfer level (RTL) circuit design stage, including: obtaining clock gating information defined in a clock gating (CG) specification according to a clock gating format, wherein the clock gating information describes a target clock gating behavior of at least a first gated clock signal utilized by an integrated circuit design, the CG specification comprises a template structure defining a relationship between an output gated clock and an input clock, based on an enable condition, and a top mapping associating top level signals, including the first gated clock signal, of the integrated circuit design to the template structure; and automatically generating a first clock gating (CG) checker to verify a clock gating behavior, based on an expected output time and an expected gated time during testing of the integrated circuit design.

Abstract: Embodiments of devices and method for detecting semiconductor substrate thickness are disclosed. In an embodiment, an IC device includes a semiconductor substrate, a charge emitter embedded in the semiconductor substrate and configured to produce an electrical charge in the semiconductor substrate and a charge sensor embedded in the semiconductor substrate and configured to generate a response signal in response to the electrical charge produced in the semiconductor substrate. The magnitude of the response signal depends on the thickness of the semiconductor substrate.

Abstract: Embodiments of a charge pump circuit and a method for operating a charge pump circuit are disclosed. In an embodiment, a charge pump circuit includes a charge pump configured to generate a charge pump output voltage, a transistor array including multiple transistor devices that includes at least one transistor device having a back gate terminal coupled to the charge pump output voltage, and a control circuit configured to control the charge pump output voltage so as to regulate the back bias voltage of the transistor devices within the transistor array. Other embodiments are also described.

Abstract: An apparatus comprising a power providing arrangement for a field powered device having a coil antenna for receiving a wireless signal, the power providing arrangement comprising: a first capacitor configured to be coupled to the coil antenna, the first capacitor configured to store energy obtained from the wireless signal received by the coil antenna, up to a first stored energy level, and configured to provide said energy to power the field powered device; a second capacitor arranged in parallel with the first capacitor via a switch; the switch providing at least a connected state in which the first capacitor and the second capacitor are connected in parallel and configured to both store the energy obtained from the wireless signal up to a second stored energy level, greater than the first stored energy level, and configured to provide said energy to power the field powered device and a disconnected state in which the second capacitor is disconnected from the first capacitor; the switch configured to tra

Abstract: Methods for fabricating crack resistant Microelectromechanical (MEMS) devices are provided, as are MEMS devices produced pursuant to such methods. In one embodiment, the method includes forming a sacrificial body over a substrate, producing a multi-layer membrane structure on the substrate, and removing at least a portion of the sacrificial body to form an inner cavity within the multi-layer membrane structure. The multi-layer membrane structure is produced by first forming a base membrane layer over and around the sacrificial body such that the base membrane layer has a non-planar upper surface. A predetermined thickness of the base membrane layer is then removed to impart the base membrane layer with a planar upper surface. A cap membrane layer is formed over the planar upper surface of the base membrane layer. The cap membrane layer is composed of a material having a substantially parallel grain orientation.

Abstract: A memory system comprises an SRAM array and a NVM array. The SRAM array and NVM array are both organized in rows and columns. The NVM array is directly coupled to the SRAM array. The memory system may also be coupled to a system bus of a data processing system. The number of columns of the NVM array is an integer multiple of the number of columns of the SRAM array, where the integer multiple is greater than one. Column logic is coupled to the SRAM array and to the NVM array. The column logic controls accesses to the SRAM and to the NVM array, and the column logic controls direct data transfers between the SRAM array and the NVM array.

Abstract: An embodiment of a distributed amplifier includes an output collection line, a plurality of tap nodes distributed along the output collection line, and a plurality of amplification paths coupled to the tap nodes. An embodiment of an amplification path includes an amplifier and a compensation circuit. The amplifier is configured to receive and amplify an input RF signal to produce an amplified RF signal at an amplifier output. A compensation circuit input is electrically coupled to the amplifier output, and a compensation circuit output is electrically coupled to one of the tap nodes. The compensation circuit includes a series inductance electrically coupled between the compensation circuit input and the compensation circuit output, and a shunt capacitance electrically coupled between the series inductance and a ground reference node. The amplifiers and the compensation circuit may be monolithically implemented on a single substrate, or may be implemented on separate substrates.

Abstract: A multi-die sensor system comprises a package and one or more transducer dies mounted in the package. Each transducer die includes one or more transducers, a temperature control element, and temperature sensor. The temperature control element changes the temperature of at least a portion of the transducer during operation of the temperature control element. A temperature sensor senses the temperature of at least the portion of the transducer. An output circuitry die mounted in the package receives transducer signals and a sensed temperature signal from the temperature sensor.

Abstract: An optimized hardware architecture and method introducing a simple arithmetic processor that allows efficient implementation of an Elliptical Curve Cryptography point doubling algorithm for Jacobian coordinates. The optimized architecture additionally reduces the required storage for intermediate values.

Abstract: In an embodiment, an integrated circuit (IC) device for detecting fault attacks is disclosed. In the embodiment, the IC device includes a main CPU core, memory coupled to the main CPU core, and a co-processor core including a checksum generation module, the co-processor core coupled to the main CPU core, wherein the main CPU core is configured to direct the co-processor core to process data from the memory and the co-processor core is configured to process the data, in part, by feeding internal signals to the checksum generation module and wherein the co-processor core is further configured to return a checksum value generated by the checksum generation module to the main CPU core.

Abstract: In one aspect, a buffer circuit comprises a source or emitter follower input stage and output stage. A load is provided between the stages which comprises a representation of an output load of the buffer circuit. This improves the circuit linearity whilst enabling a high input impedance to be obtained. In another aspect, a buffer circuit comprises a source or emitter follower output stage. A load is in the form of a filter is provided and which comprises a representation of an output load of the buffer circuit.

Abstract: A method for circuit layout migration comprises creating a list of layout components in a source layout; determining a plurality of first groups of layout components being regularly aligned horizontally or vertically; determining first subsets of layout components which each belong to at least two of a respective set of determined first groups; determining a plurality of second groups of layout components, each second group comprising mutually exclusive ones of the first subsets of layout components; determining symmetry axes for pairs of second groups; building a constraint graph of the layout components of the source layout using alignment constraints for the alignment of layout components within each of the second groups and distance constraints for preserving a regularity pattern within each of the second groups and symmetry constraints for the determined symmetry axes for pairs of second groups; and performing constraint-graph-based compaction of the source layout.

Abstract: Embodiments of sensing devices include one or more integrated circuit (IC) die, a housing, and a fluid barrier material. Each IC die includes an electrode-bearing surface and a contact surface. One of the die includes an SFET with a sensing electrode proximate to the electrode-bearing surface. The same or a different die includes a reference electrode proximate to the electrode-bearing surface. The die(s) also include IC contacts at the contact surface(s), and conductive structures coupled between the SFET, the reference electrode, and the IC contacts. The housing includes a mounting surface, and housing contacts formed at the mounting surface. The IC contacts are coupled to the housing contacts. The fluid barrier material is positioned between the mounting surface and the IC die. The fluid barrier material provides a fluid barrier between the IC and housing contacts and a space that encompasses the sensing electrode and the reference electrode.