Abstract: A data processing system includes a module for generating and distributing random masks to a number of cryptographic accelerators while providing for fewer total interconnects among the components generating the random masks. The module segments the tasks associated with generating random masks across a number of modules and blocks such that routing and timing problems can be minimized and layout can be optimized. A method for generating and distributing random masks to a number of cryptographic accelerators is also provided. The random masks are utilized by cryptographic accelerators to protect secret keys, and data associated with those keys, from discovery by unauthorized users.

Abstract: A semiconductor device comprising a bipolar transistor and a method of making the same. The bipolar transistor includes a collector having a laterally extending drift region. The bipolar transistor also includes a base located above the collector. The bipolar transistor further includes an emitter located above the base. The bipolar transistor also includes a reduced surface field (RESURF) gate located above an upper surface of the laterally extending drift region for shaping an electric field within the collector. The bipolar transistor further includes a gap located between the reduced surface field gate and an extrinsic region of the base of the device, for electrically isolating the reduced surface field gate from the base. A lateral dimension Lgap of the gap is in the range 0.1 ?m?Lgap?1.0 ?m.

Abstract: Consistent with an example embodiment, a user (touch screen) interface has haptic feedback. The user interface comprises, a substrate, a transparent bottom electrode on top of the substrate, a transparent wrinkling layer on top of the transparent bottom electrode, a transparent top electrode on top of the transparent wrinkling layer; and a transparent protective surface on top of the transparent top electrode. The transparent wrinkling layer changes from a smooth surface to a roughened surface upon application of a voltage between the top electrode and the bottom electrode; the voltage generates an electrostatic force mutually attracting the top and bottom electrodes to exert a compressive force upon the transparent wrinkling layer sufficient to generate a degree of surface wrinkling that is perceptible to the touch.

Abstract: An error-resilient memory device includes sets of memory blocks and redundant memory blocks for storing a set of data bits. A memory block includes a set of memory cells, each memory cell is adjacent to at least two other memory cells, and a memory block is formed by a matrix of the set of memory cells. In a row-folded implementation, a word line is connected to each memory cell, and a set of bit lines is connected to the corresponding set of memory cells. In a column-folded implementation, a bit line is connected to each memory cell, and a set of word lines is connected to the corresponding set of memory cells. A redundant memory block is used to store the set of data bits when the memory block includes a fault.

Abstract: A system on chip having two or more responder units and two or more protection units is provided. Each of the responder units comprises a set of responder elements. Each of the protection units is associated with and protects one of the responder units and is arranged to provide a group mapping. The group mapping assigns one or more group identifiers to each of the responder elements of the respective responder unit.

Abstract: A buffer circuit includes a first capacitor having a first terminal coupled to receive an input signal, a second capacitor having a first terminal coupled to the first terminal of the first capacitor, and a latching portion coupled to a second terminal of the first capacitor and a second terminal of the second capacitor. The latching portion provides an output signal. A first transistor includes a control electrode coupled to receive the output signal, a first current electrode coupled to a first bias voltage supply terminal, and a second current electrode coupled to the second terminal of the second capacitor.

Abstract: In a processing system, a method includes selecting, at a timer management component of a processor, a timer ring of a set of timer rings for a requested timer based on a time unit granularity associated with the requested timer, wherein each timer ring of the set has a different time unit granularity. The method further includes instantiating the requested timer in a selected entry of the selected timer ring. Instantiating the requested timer may include fixedly maintaining a record for the requested timer in the selected entry of the selected timer ring for the entire time span of the requested timer.

Abstract: A method generates scan patterns for testing an electronic device called DUT having a scan path. A scan tester is arranged for executing a scan shift mode and a capture mode. A scan test interface has a clock control unit for stretching a shift cycle of the scan clock in dependence of a scan clock pattern. The method determines at least one power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode, and generates, in addition to the scan pattern, a scan clock pattern indicative of stretching the power shift cycle. Advantageously, a relatively high scan shift frequency may be used while avoiding detrimental effects of said voltage drop by extending the respective power shift cycle, whereby test time and yield loss are reduced.

Abstract: One example discloses a communications device, including: a bio-antenna conducting surface configured to receive a set of bio-antenna modulated broadcast signals; wherein the conducting surface is configured to receive the set of bio-antenna modulated broadcast signals through a capacitively coupling; a broadcast receiver coupled to the conducting surface; and wherein the conducting surface is configured to pass the broadcast signals to the broadcast receiver.

Abstract: One example discloses an apparatus for voice communication, including: a first wireless device including a first pressure sensor having a first acoustical profile and configured to capture a first set of acoustic energy within a time window; wherein the first wireless device includes a near-field magnetic induction (NFMI) signal input; wherein the first wireless device includes a processing element configured to: receive, through the NFMI signal input, a second set of acoustic energy captured by a second pressure sensor, having a second acoustical profile, within a second wireless device and within the time window; apply a signal enhancement technique to the first and second sets of acoustic energy based on the first and second acoustical profiles; and output an enhanced voice signal based on applying the signal enhancement.

Abstract: Various circuits, apparatuses and methods are disclosed for generating a DC voltage conversion. In an example embodiment, an apparatus includes a DC voltage multiplier having a first capacitor. In a first mode, the first capacitor is charged to store a first voltage between first and second terminals of the capacitor. In a second mode, the DC voltage multiplier shifts a voltage of the second terminal up to a second voltage, thereby shifting the first terminal to a third voltage. The apparatus also includes a fractional output control circuit that when enabled, connects a second capacitor between the first terminal of the first capacitor and the ground reference voltage. The connecting of the second capacitor causes the first terminal of the first capacitor to be pulled down to a voltage between the first and third voltages when the second terminal is shifted up to the second voltage.

Abstract: Corrections are provided for mismatches between an in-phase (I) signal and a quadrature-phase (Q) signal, the I and Q signals having a first frequency band. A frequency filter circuit filters the I and Q signals to produce a filtered I and Q output with a second frequency band that is a subset of the first frequency band. Digital circuitry includes a multiple-tap correction filter having a plurality of taps and configured to generate I and Q output signals by filtering the I and Q signals according to respective sets of coefficients for the plurality of taps. A coefficient estimator generates the sets of coefficients relative to different frequency bands.

Abstract: An active I/Q generator circuit comprises an input node for receiving a reference oscillation signal. The circuit has an I-output and a Q-output for respectively outputting an I-signal and a Q-signal. A first active component is electrically coupled to the input node and arranged to amplify the reference oscillation signal and to output an amplified reference oscillation signal. A second active component is electrically coupled to the first active component to receive the amplified reference oscillation signal. The second active component is arranged to generate, based on the amplified reference oscillation signal, an in-phase signal and a, with respect to the in-phase signal, phase shifted signal, the second active component electrically coupled to the in-phase signal output for providing the in-phase signal and electrically coupled to the quadrature-phase output for providing the phase-shifted signal.

Abstract: A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements located in a plane of the magnetic field sensor. Each sense element comprises a pinned layer and a sense layer. The pinned layer has a reference magnetization oriented parallel to the plane and the sense layer has a sense magnetization oriented out-of-plane. A permanent magnet layer may be spaced apart from the sense elements which magnetically biases the sense magnetization of the sense layer into an out-of-plane direction that is non-perpendicular to the plane of the sensor. The sense magnetization is orientable from the out-of-plane direction toward the plane of the sensor in response to an external magnetic field. The permanent magnet layer enables detection of the external magnetic field in a sensing direction that is also perpendicular to the plane of the magnetic field sensor.

Abstract: Apparatus and methods for operating a read-only memory (ROM) are disclosed. The method for operating the ROM includes sensing a dummy bit line with a dummy sense amplifier coupled to the dummy bit line to generate a keeper adjust signal. Based on the keeper adjust signal, a keeper strength of a keeper circuit coupled to a sense amplifier circuit is adjusted. The sense amplifier circuit is capable of sensing data stored in the ROM.

Abstract: A display control unit is connected to a display and arranged to generate a video signal representing a sequence of video frames to be displayed consecutively on said display. The display control unit may include a first memory unit arranged to buffer a set of image descriptors; a second memory unit connected between said first memory unit and said display; an update unit connected to said first memory unit and arranged to update said image descriptors in said first memory unit and to generate a proceed signal only when said set of image descriptors in said first memory unit is up to date; a copy unit arranged to copy said image descriptors from said first memory unit to said second memory unit in response to said proceed signal; and a video unit arranged to generate said video signal on the basis of said image descriptors in said second memory unit.

Abstract: A receiving apparatus for SNR estimation of a signal such as the LTE PUCCH, transmitted over a channel of an OFDM wireless communication system. The proposed apparatus brings determines the noise power level in the frequency domain based on a noise covariance matrix where timing errors are back compensated in the equation since timing error is expressed a complex exponential therein. Contrary to the common methods used for determining the noise power level, in the present invention deriving the channel estimate components from the pilot symbol(s) comprised in the received signal is not required. Based on the present invention, user's transmit power is reduced thereby improving battery power longevity. Further, since interference is reduced, more users may be multiplexed together in the same resources. A method and a computer program product are also claimed.

Abstract: One embodiment of making a diode includes forming a first electrode to which an electric field is applied; forming a second electrode to which the electric field is applied; and forming a vapor gap region between the first electrode and the second electrode. A total capacitance measured between the first electrode and the second electrode varies based on presence of a polar vapor species on at least a portion of an electrode surface of at least one of the first electrode and the second electrode.

Abstract: A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

Abstract: An approach is provided in which an endianness violation detection sub-system detects endianness violations between hardware units. The endianness violation detection sub-system tracks memory operations performed by multiple hardware units via debug channels and generates lookup table entries that are stored in a lookup table. When the endianness violation detection sub-system detects endianness relevant load attributes of a load operation that are different than corresponding endianness relevant store attributes of a store operation, the endianness violation detection sub-system generates an endianness violation. In one embodiment, the endianness violation detection sub-system identifies an endianness violation when the endianness violation detection sub-system detects a difference in the byte ordering type between a hardware unit performing a store operation and a hardware unit performing a load operation.