Abstract: Aspects of various embodiments of the present disclosure are directed to applications utilizing voltage sampling. In certain embodiments, a sample and hold circuit is configured to sample voltages that exceed a tolerance voltage of components. The circuit includes a first and a second capacitors. In a first mode, a voltage difference between an input node and a first reference voltage is sampled using the first capacitor. Also in the first mode, a voltage stored by the second capacitor is referenced to a second reference voltage and provided to a first output node. In a second mode, a voltage difference between an input node and a first reference voltage is sampled using the second capacitor. Also in the second mode, a voltage stored by the first capacitor is referenced to the second reference voltage and provided to a second output node.

Abstract: One example discloses a system for filtering digital certificates within a communications network, comprising: a first set of network-nodes, having a first attribute and a respective first set of digital certificates; a second set of network-nodes, having a second attribute and a respective second set of digital certificates; and a digital certificate authority, having a digital certificate validity list which includes the first and second sets of digital certificates; wherein the certificate authority filters the validity list based on the first attribute and transmits the filtered validity list to the first set of network nodes. Another example discloses a method for filtering digital certificates, comprising: maintaining a digital certificate validity list; identifying a set of network-nodes, having an attribute; filtering the validity list based on the attribute; and transmitting the filtered validity list to the set of network-nodes.

Abstract: Disclosed is a flexible insert (100) for placement on the human eye, comprising a light source (110) in said insert such that light emitted from the light source is shielded from the human eye upon correct placement of the insert on the human eye, a light-responsive material (120) placed in the light path of the light source, said light-responsive material emitting light upon stimulation by the light from said light source, the intensity of said stimulated emission being sensitive to a chemical interaction of the light-sensitive material with an analyte of interest, a photodetector (130) for detecting the light emitted by the light-responsive material; and a transmitter (140) coupled to the photodetector for transmitting a photodetector reading. The insert may be used in conjunction with a reader for automated monitoring of an analyte of interest such as glucose in the tear fluid of its wearer.

Abstract: One example discloses a substance detection device, including: a substrate configured to carry a substance; wherein the substrate has a length and a substance loss along the length of the substrate; a test region coupled to the substrate and configured to bond to at least a portion of the substance; a sensor coupled to the substrate at a fixed location along the length and having a sensing signal output; an integration circuit coupled to the sensor and configured to integrate, over a time interval, a signal from the sensing signal output; and a detection circuit coupled to the integration circuit and configured to output a substance detected signal if the integrated sensing signal output signal deviates from the substance loss corresponding to the fixed sensor location.

Abstract: Various aspects are directed to the detection of tampering, as may be applicable to retail goods and a variety of implementations. As may be consistent with one or more embodiments, an apparatus includes a loop conductor having first and second ends and contiguous conductive material extending in a loop between the ends. A detection circuit detects continuity of the loop conductor and characteristics of power that is provided to the loop conductor and is indicative of validity of the continuity detection. A communication circuit communicates a wireless signal indicative of the detected electrical characteristics, and an energy circuit powers the loop conductor, detection circuit and communication circuit via received wireless power. Other aspects are further directed to an interrogator that provides the wireless power and evaluates the wireless signal to detect tampering with the conductive loop and validity thereof.

Abstract: Transients caused by load modulation can fee compensated far by adjusting pulse shapes. A radio frequency (RP) carrier signal can be modulated using load modulation. For the modulated RF carrier signal a particular pattern can be detected for a symbol period that precedes a second symbol that does not use load modulation. In response to the detecting, a pulse shape of the first symbol can be adjusted to mitigate the transients.

Abstract: To promote ease of use, as well as a reduction in bit error rates during extended data exchange between a coupled NFC tag/reader pair, signal strength is measured from a plurality of NFC tag antennas each positioned differently with respect to a common reader field, and differences in signal strength are used to determine an optimum positioning of the tag, or tag emulator, with respect to the reader. Alternative embodiments may include signal time of flight for determining orientation of the NFC antennas within the reader field. Information is generated by the tag, or tag emulator, and output by the tag, or tag emulator, such that a user may direct the positioning of the tag, or tag emulator, for improved communication with the reader.

Abstract: A magnetic field sensor comprises a sensor bridge having multiple sensor legs. Each sensor leg includes magnetoresistive sense elements, each comprising a pinned layer having a reference magnetization parallel to a plane of the sensor and a sense layer having a sense magnetization that is skewed away from three orthogonal axes. The sense magnetization of a portion of the sense elements is oriented in a first direction and the sense magnetization of a different portion of the sense elements is magnetically biased in a second direction by a permanent magnet layer. The second direction differs from the first direction by an opposing angular magnitude to yield a balanced sensor bridge that produces a zero-offset outcome in the absence of an external magnetic field.

Abstract: In one embodiment, a sense amplifier circuit includes two current paths. Each path includes a transistor configured as a current source during a memory read operation and a second transistor. During the first phase of a memory read operation, the first current path is coupled to one cell and the second current path is coupled to a second cell. The sense amplifier circuit includes a capacitor that during a first phase of a memory read operation, is coupled between two corresponding nodes of the two paths to store a voltage difference between the two nodes. During the second phase, the cell/current path couplings are swapped and the capacitor is coupled to the control terminal of one of the second transistors to control the conductivity of the transistor for adjusting a voltage of an output node to indicate the value of the data being read.

Abstract: An electronic device that includes a sensor module, a measuring module and a near field communication (NFC) device. The sensor module receives an input signal. The measuring module measures the strength of the input signal and determines whether the input meets a predefined threshold. If the strength of the input signal meets the predefined threshold, the measuring module activates the NFC device. If the strength of the input signal does not meet the predefined threshold, the measuring module de-activates the NFC device.

Abstract: A sense amplifier circuit includes a sampling capacitor coupled to the input of an inverting amplifier. The output of the inverting amplifier is coupled to a transistor that includes a current terminal. The memory read operation includes two phases. During a first phase, a terminal of the capacitor is coupled to a first cell. During a second phase, the terminal of the capacitor is coupled a second cell.

Abstract: A homogeneity detection circuit, a valve driving system, a vehicle, an integrated circuit and a method of homogeneity detection in a valve driving system are provided. The homogeneity detection circuit comprises a first input, a second input and a comparison circuit. The first input receives a first signal being related to a first driving signal for driving a first valve. The second input receives a second signal being related to a second driving signal for driving a second valve. The comparison circuit compares the first signal with the second signal and generates a warning signal if predetermined differences are detected between the first driving signal and the second driving signal.

Abstract: A system for measuring high power currents, including: a low power transistor that is a scaled replica of a high power transistor of a high power driver; a regulator connected to the low power transistor, wherein the regulator is configured to regulate the current flowing through the low power transistor based upon a voltage sensed across the high power transistor and a chop signal; a current mirror with an input connected to the regulator and an output; a current detector having in input configured to receive the chop signal, wherein the current detector is connected to the output of the current mirror and wherein the current detector is configured to measure the current at the output of the current mirror to produce an estimate of the current flowing through the high power transistor.

Abstract: A data processing system includes a processor core and a hardware module. The processor core performs tasks on data packets. The ordering scope manager stores a first value in a first storage location. The first value indicates that exclusive execution of a first task in a first ordering scope is enabled. In response to a relinquish indicator being received, the ordering scope manager stores a second value in the first storage location. The second value indicates that the exclusively execution of the first task in the first ordering scope is disabled.

Abstract: A system for providing a first voltage generated by a main supply and a second voltage generated by a battery to an integrated circuit (IC) includes supply-selection, control logic and switching circuits. The supply-selection circuit includes first, second, and third transistors. The switching circuit includes fourth and fifth transistors that supply the first and second voltages to the IC when switched on. The supply-selection circuit selects and provides the higher of the first and second voltages to body terminals of the fourth and fifth transistors for maintaining required body-bias voltage conditions. The control logic circuit generates a first control signal as long as the first voltage is within a predetermined range for keeping the fourth transistor switched on and a second control signal when the first voltage is not within the predetermined range for switching on the fifth transistor to supply the second voltage.

Abstract: A two-stage context adaptive binary arithmetic coding (CABAC) parser is provided to efficiently transcode an input video bitstream that is partitioned into tiles into a non-tiled based video bitstream. A picture of the input video bitstream is partitioned into one or more tiles, each of which has multiple coding tree units (CTUs) according to the HEVC standard. The two-stage CABAC parser parses the input video bitstream in tile scan order in the first stage and generates a list of identified CTUs, whose CABAC state data are saved for the second stage parsing. In the second stage parsing, the two-stage parser parses the same input video bitstream in raster scan order using the saved CABAC state data of the identified CTUs.

Abstract: A low power clock distribution circuit system (200) includes a clock generator (201) for generating a high frequency clock signal that is supplied to a clock interconnect running to multiple lanes of an integrated circuit, each lane including a passive clock repeater circuit (e.g., 203) having a differential-mode RLC network (e.g., 301) that is shielded by an active guard ring structure (e.g., 511) and that is coupled to receive first and second input clock signals (Vip, Vin) to provide clock signal gain boosting at a predetermined frequency range and clock signal attenuation out of the operating frequency range, thereby generating the first and second output clock signals (Vop, Von) that are provided to a clocked circuit (e.g., 211).

Abstract: A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.

Abstract: A method and information processing system with improved cache organization is provided. Each register capable of accessing memory has associated metadata, which contains the tag, way, and line for a corresponding cache entry, along with a valid bit, allowing a memory access which hits a location in the cache to go directly to the cache's data array, avoiding the need to look up the address in the cache's tag array. When a cache line is evicted, any metadata referring to the line is marked as invalid. By reducing the number of tag lookups performed to access data in a cache's data array, the power that would otherwise be consumed by performing tag lookups is saved, thereby reducing power consumption of the information processing system, and the cache area needed to implement a cache having a desired level of performance may be reduced.

Abstract: A memory cell includes a first bidirectional resistive memory element (BRME), and a second BRME, a first storage node, and a second storage node. A resistive memory write to the cell includes placing the first BRME and the second BRME in complementary resistive states indicative of the value being written. During a subsequent restoration operation, the value as written in the first BRME and second BRME is written to the first storage node and the second storage node while a wordline connected to the memory cell is deasserted.