Abstract: An integrated circuit (IC) having a heat-generating element, such as a power MOSFET, a current-carrying conductor coupled to the heat-generating element, a sense conductor adjacent the current-carrying conductor, and a failure-detection circuit coupled to the sense conductor. When thermal cycling of the IC causes the resistance of the sense conductor to become greater than a temperature-dependent threshold value, the failure-detection circuit generates a signal indicating that the integrated circuit will soon fail. The resistance of the sense conductor is determined by injecting a current into the sense conductor to generate a voltage. The temperature-dependent threshold value is a voltage generated by injecting a current into a reference conductor disposed away from the current-carrying and sense conductors. A voltage comparator compares the two voltages to generate the output.

Abstract: A sensor circuit, including at least a first sensor arranged to selectively receive a first test current; a first digital-to-analog converter, DAC, arranged to receive a first signal from the first sensor and output a first compensation signal in response thereto; a second DAC arranged to receive a second signal from a second sensor and output a second compensation signal in response thereto; and a controller operably coupled to the first and second DACs and operable to determine from at least one of: the first compensation signal and second compensation signal whether a short condition exists between the first sensor and the second sensor.

Abstract: A protection unit of an interrupt stack accessible by a CPU controlled by one software program, for storing and removing stack frame(s), the stack protection unit being coupleable to the stack and the CPU, comprising: a processor coupled to a first and a second address register; wherein, when a first stack frame is stored onto the stack and the execution of the software program is suspended by the CPU, responsive to one or more occurring hardware IRQs; the processing unit is adapted to set one access rule based on the first and second address registers, preventing: the occurring ISR to be serviced, from accessing a hardware-protected region of the stack, comprising at least the first stack frame and at least one stack frame associated with one or more suspended IRQs. A processor, a method and a computer program are also claimed.

Abstract: Various embodiments relate to a bias generator including: a bias generator circuit; a master startup circuit that applies current to a first node in the bias generator circuit; a second startup circuit that applies current to additional nodes in the bias generator circuit; and a power switch that receives a power from a power supply and that provides power to the bias generator circuit, the master startup circuit, and the second startup circuit.

Abstract: A MEMS electrostatic actuator comprises first and second opposing electrode arrangements, wherein at least one of the electrode arrangements is movable. A dielectric material (24) is adjacent the one of the electrode arrangements (22). The second electrode arrangement is patterned such that it includes electrode areas (26) and spaces adjacent the electrode areas, wherein the dielectric material (24) extends at least partially in or over the spaces. The invention uses a multitude of electrode portions as one plate. The electric field lines thus form clusters between the individual electrode portions and the opposing electrode. This arrangement provides an extended range of continuous actuation and tunability.

Abstract: A system includes a processor having first and second processing units and a memory coupled to the processor. The memory includes processor executable code to implement an application to execute a first process to provide first application output information and to execute a second process to provide second application output information, a selector to provide a first indication that the first process is a critical process and a second indication that the second process is a non-critical process, and an application program interface (API) to run on the first processing unit. The API directs the processor to run the application on the second processing unit, executes the first process to provide first API output information in response to the first indication; determines if the first application output information matches the first API output information, and determines to not execute the second process in response to the second indication.

Abstract: Aspects of the present disclosure are directed to sensing apparatuses and methods. As may be implemented in accordance with one or more embodiments, analog signals are obtained from a plurality of sensors and used to provide an output for particular ones of the sensors as follows. Analog signals are obtained from a particular sensor and one or more adjacent sensors. Different weighting factors are applied to the analog signals, based on the position of the sensor or sensors. The signals with the weighting factors applied thereto are combined to provide an output signal.

Abstract: A frequency shift keying (FSK) demodulator for demodulating symbols includes correlation circuits configured to output correlation metrics based on a buffered portion of an input signal as the input signal is continuously received by the FSK demodulator. The FSK demodulator also includes a result combining stage configured to output a set of first correlation results based on correlation metrics generated for a first portion of the input signal encoding a current symbol and at least one past symbol, and a set of second correlation results based on correlation metrics generated for a second portion of the input signal encoding the current symbol and at least one next symbol; and a time combining stage configured to combine a set of delayed first correlation results with the set of second correlation results to produce a demodulation decision that returns a most likely symbol value for the current symbol.

Abstract: A multichip radar system is disclosed, comprising a plurality of configurable ICs, and a digital interface therebetween, each configurable IC being configurable to operate as a master IC and as a slave IC. The configurable ICs may be similar or identical, and have an allocated measurement range. Each configurable IC comprises: a down-converter; an ADC; a digital signal processor; and a transmitter to transmit a radar signal. One is configured as a master IC and to transmit a radar signal and each of the other configurable ICs to operate as a slave IC. Each configurable IC is adapted to use a common Local Oscillator signal, a common clock signal, and a common timing signal for determining at least the start of the common sampling window. A method of operating such a multichip radar system is also disclosed, as is a configurable IC or radar IC suitable for such a system.

Abstract: Interfacing according to a common public radio interface in a base station in a mobile communication system is described. The interfacing comprises a conversion process for rate-converting legacy data samples. First a predetermined number of the legacy data samples is converted to frequency samples in a frequency domain, then the frequency samples are zero padded to extend the frequency range according to a related sample rate of a 4G data format and then converted into a number of data samples of the related sample rate. The related sample rate is a multiplication of S/K times a basic frame rate of the 4G data format, S samples being allocated to K frames, K and S being integers and K being 8 or less. Advantageously large buffers for allocating a large number of legacy samples to 4G frames are avoided.

Abstract: A noise suppression circuit comprises a switchable transistor and an amplifier having a first amplifier input terminal electrically coupled to an output terminal of the switchable transistor for sensing a voltage thereat, and an amplifier output terminal electrically coupled to a control terminal of the switchable transistor for outputting a control voltage thereto.

Abstract: A squelch detector, including: an input configured to receive an input signal; a peak detector connected to the input configured to detect a maximum value of the input signal wherein the peak detector includes a refresh input configured to receive a refresh signal to refresh the output of the peak detector, a valley detector connected to the input configured to detect a minimum value of the input signal wherein the valley detector includes a refresh input configured to receive the refresh signal to refresh the output of the valley detector, and a comparator including a first signal input connected to an output of the peak detector, a second input connected to an output of the valley detector, and a first reference input, wherein the comparator is configured to compare a difference between an output of the peak detector and an output of the valley detector and a reference value received at the first reference input and configured to produce an output based upon the comparison.

Abstract: Techniques are described herein that transfer information using a container-located module. The module is coupled to sensor(s) that are configured to detect characteristic(s) pertaining to a medical substance that is included in a medical container. The module wirelessly transfers information that is based on the characteristic(s) to a requesting device in response to a request from the requesting device.

Abstract: At least one embodiment of a correlator comprising a plurality of correlator taps is configurable to provide synchronization and symbol modulation for a plurality of modulation systems. Among other uses, at least one embodiment of the correlator can provide a coarse symbol timing value. In response to determining the coarse symbol timing value, a receiver can receive a signal. Among other uses, at least one embodiment of the correlator can provide a carrier frequency offset (CFO) estimate. In response to determining the CFO estimate, a receiver can receive a signal.

Abstract: A method of starting-up a switched reluctance, SR, motor is provided. The method comprises simultaneously energizing a plurality of phases at a first time point with respective phase voltages that are substantially the same, until the motor rotor is stabilized in alignment with either one of the plurality of phases; simultaneously de-energizing the plurality of phases at a second time point that follows the first time point; monitoring a decrease of respective phase currents in the plurality of phases from a third time point that follows the second time point by a first predetermined time interval; determining a phase of alignment of the rotor using evaluation of the decrease of the phase currents following simultaneous de-energizing of the plurality of phases; and, initiating rotation of the rotor from the determined phase of alignment of the rotor.

Abstract: Each processor of a plurality of processors is configured to execute an interrupt message instruction. A message filtering unit includes storage circuitry configured to store captured identifier information from each processor. In response to a processor of the plurality of processors executing an interrupt message instruction, the processor is configured to provide a message type and a message payload to the message filtering unit. The message filtering unit is configured to use the captured identifier information to determine a recipient processor indicated by the message payload and, in response thereto, provides an interrupt request indicated by the message type to the recipient processor.

Abstract: Embodiments of a method for clock synchronization in a radio frequency identification (RFID) equipped device, an RFID equipped device, and a hand-held communications device are described. In one embodiment, a method for clock synchronization in an RFID equipped device involves measuring a difference between a field clock frequency generated from an external clock and an internal clock frequency generated from an internal clock and generating outgoing bits in the RFID equipped device in response to the measured difference. Generating the outgoing bits involves adjusting the bit length of at least one of the outgoing bits in response to the measured difference. Other embodiments are also described.

Abstract: A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.

Abstract: A method and apparatus for generating an indicator of a risk level in motor vehicle and notifying vehicle systems when a risk level is above a specific threshold includes, receiving a plurality of driver distraction indicators, assigning a weighting value to each indicator, applying a scaling factor to the weighting value assigned to those indicators which are identified as being related, and summing the weighting values to produce an output value indicating a risk level. Distraction indicators can include on-board system and sensor outputs and stored data relating to driver attributes. Related indicators may comprise those distraction indicators relating to environmental conditions (eg. rain and low ambient light levels), or to vehicle performance to driver concentration level (eg. in-car phone and navigation system). The scaling step allows the weighting process to be refined based on the status of other received indicators.

Abstract: Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.