Abstract: One example discloses an open-circuit detector, comprising: a first current source configured to inject a current at an output of a closed-loop circuit; a detector configured to monitor a voltage of the closed-loop circuit; wherein the detector is configured to indicate whether the voltage monitored exceeds a predetermined threshold voltage; a controller configured to regulate the current injected by the first current source; wherein the controller is configured to set an open-circuit flag if the current injected caused the voltage to exceed the predetermined threshold voltage.

Abstract: In an optocoupler circuit, a first direction path, which transmits signals from a first to a second terminal, includes a first level shifter, a second level shifter, and a first optocoupler. The first level shifter receives a first input signal at the first terminal, and shifts a voltage level of the first input signal to a first shifted voltage level with respect to a first ground level in a first power domain, to provide a first shifted signal. The first optocoupler receives the first shifted signal, and generates a first optocoupler signal in response to the first shifted signal. The second level shifter receives the first optocoupler signal, and shifts a voltage level of the first optocoupler signal to a second shifted voltage level with respect to a second ground level in a second power domain, to provide a second shifted signal at the second terminal.

Abstract: One example discloses a near-field interface device, including: a near-field antenna; a physical port configured to be coupled to a computer; a controller coupled to the antenna and the physical port; wherein the controller is configured to translate a near-field signal received from the near-field antenna into an input command generated by a user; and wherein the controller is configured to transmit the input command to the computer through the physical port.

Abstract: A method and apparatus are described for compensating input voltage ripples of an interleaved boost converter using cycle times. In an embodiment, a phase compensator receives a first duty cycle measurement of a first converter and a second duty cycle measurement of a second converter, compares the first duty cycle to the second duty cycle and generates a phase compensation in response thereto. A phase combiner combines a phase adjustment output and the phase compensation and produces a phase control output, and a cycle controller is coupled to the first and the second converters to generate a first drive signal to control switching of the first converter and to generate a second drive signal to control switching of the second converter, wherein a time of the second drive signal is adjusted using the phase control output.

Abstract: A Controller Area Network (CAN) system, method, and circuit are provided with a dual mode bus line termination circuit connected between signal lines of a serial bus and optimized for both differential and single-ended communication modes over the serial bus, where the dual mode bus line termination circuit includes first and second resistance termination paths connected in parallel between first and second bus wires of the serial bus to provide an odd mode termination impedance (RODD) that matches an impedance of the serial bus when operating in the differential communication mode, and to also provide an even mode termination impedance (REVEN) that matches an impedance of the serial bus when operating in the single-ended communication mode.

Abstract: A waveguide antenna (200) is disclosed, comprising: a first plurality (220) of slots (222,224), for producing a beam having a first radiation pattern (301) at a first resonant frequency (f1); and a second plurality (230) of slots (232, 234), for producing a beam having a second radiation pattern (302) at a second resonant frequency (f2).

Abstract: A method for cartesian (IQ) to polar phase conversion includes: converting a first input value into a first absolute value, and a second input value into a second absolute value; converting the first absolute value into a first logarithmic value by calculating a scaled logarithmic value of the first absolute value, and the second absolute value into a second logarithmic value by calculating a scaled logarithmic value of the second absolute value; subtracting the first logarithmic value from the second logarithmic value, to provide a subtract value; and selecting a phase value from a plurality of phase values stored in a storage unit. Each of the plurality of phase values corresponds to a respective index value, and the phase value is selected taking the subtract value as the index value.

Abstract: A low power temperature detection method, system, and apparatus sense when a temperature threshold is reached by connecting a current conveyor (111) with a startup bias circuit (112) having a first FET (P1) (connected to level shift a reference voltage to provide an input voltage VS1), a first diode-connected BJT (Q0) (connected to generate a base-emitter voltage based on the junction temperature), and a second FET (P2) (connected to level shift the base-emitter voltage), where the startup bias circuit (112) selectively connects the current conveyor (111) to ground to form a closed loop that is activated only when an emitter current at the first diode-connected BJT (Q0) enters a self-turned-on operation region, thereby activating the current conveyor to detect a temperature threshold being reached by the device junction temperature.

Abstract: An apparatus in which electric power is generated for an electrical load from differentials in electric field strengths within a vicinity of powerlines includes: a plurality of electrodes separated and electrically insulated from one another for enabling differentials in voltage resulting from differentials in electric field strength experienced there at; and electrical components electrically connected therewith and configurable to establish one or more electric circuits whereby voltage differentials cause a current to flow through the established electric circuit for powering the electrical load.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes attaching a first end of a first bond wire to a first conductive lead and a second end of the first bond wire to a first bond pad of a first semiconductor die. A conductive lead extender is affixed to the first conductive lead by way of a conductive adhesive, the lead extender overlapping the first end of the first bond wire. A first end of a second bond wire is attached to the lead extender, the first end of the second bond wire conductively connected to the first end of the first bond wire.

Abstract: Aspects of the present disclosure are directed to radar apparatuses and methods involving the communication of data with radar signals. As may be implemented with one or more embodiments, a sequence of radar waveforms are transmitted as RF signals, the RF signals carrying communication data encoded onto a ramped radar carrier signal via phase-shift keying (PSK) modulation. Such modulation may utilize a modified, reduced-angle modulation with phase angles of less than ?. Object-reflected versions of the RF signals are received and demodulated by deramping the received object-reflected versions of RF signals using a linearized version of the radar waveforms (e.g., without PSK modulation). This approach can mitigate compression peak loss.

Abstract: A thread management circuit of a processing system stores a thread identifier table and a thread completion table. The thread management circuit receives, from a processor core, a request for execution of a portion of an application by an accelerator circuit. The thread management circuit allocates a thread identifier available in the thread identifier table to the processor core for the execution of the portion by the accelerator circuit. The thread management circuit communicates a response and an acceleration request, both including the allocated thread identifier, to the processor core and the accelerator circuit, respectively. The thread management circuit communicates a thread joining response to the processor core based on a received thread joining request and an indication by the thread completion table that the execution of the portion by the accelerator circuit is complete. The executed portion is integrated with the application based on the thread joining response.

Abstract: An integrated circuit is provided with a protected circuit wherein a first FinFET operably coupled to a signal node is protected against electrostatic discharge voltage damage by a standard cell electrostatic discharge protection circuit which is connected between first and second voltage supplies and which includes a first FinFET diode connected between the signal node and the first voltage supply, and a second FinFET diode connected between the signal node and the second voltage supply, where the first and second FinFET diodes are each formed with a FinFET device comprising (1) a body well region forming a first diode terminal connected to one of the first or second voltage supplies, and (2) a shorted gate, source, and drain regions forming a second diode terminal connected to the signal node.

Abstract: A wafer-scale die packaging device is fabricated by providing a high-k glass carrier substrate having a ceramic region which includes a defined waveguide area and extends to a defined die attach area, and then forming, on a first glass carrier substrate surface, a differential waveguide launcher having a pair of signal lines connected to a radiating element that is positioned adjacent to an air cavity and surrounded by a patterned array of conductors disposed over the ceramic region in a waveguide conductor ring. After attaching a die to the glass carrier substrate to make electrical connection to the differential waveguide launcher, a molding compound is formed to cover the die, differential waveguide launcher, and air cavity, and an array of conductors is formed in the molding compound to define a first waveguide interface perimeter surrounding a first waveguide interface interior.

Abstract: One example discloses a level-shifter circuit, comprising: a pre-driver stage configured to receive differential inputs and generate differential pre-driver outputs; a first output stage coupled to receive the differential pre-driver outputs and generate a single-ended first stage output; a second output stage coupled to receive the differential pre-driver outputs and generate a single-ended second stage output; and wherein the first and second stage outputs together form a differential output.

Abstract: A semiconductor die includes a transistor with an emitter, base, and collector. The base includes an intrinsic base that is located in monocrystalline semiconductor material grown in an opening of a first semiconductor layer. A second semiconductor layer is located above the first semiconductor layer and includes a monocrystalline portion. In some embodiments, an opening was formed in the second semiconductor layer wherein a portion of the underlying first semiconductor layer was etched to form a cavity in which a monocrystalline intrinsic base was grown.

Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.

Abstract: Embodiments of a device and a method for providing data are disclosed. In an embodiment, a device includes a processing system configured to split data of a request into messages by splitting the data based on a node of the data, where the messages fit a supported size, and provide the messages that include the data of the request to a communications interface.

Abstract: An address fault detection system includes write and read access circuits and a fault management circuit. The write access circuit receives an address and reference data for a write operation associated with a memory and parity data generated based on the reference data, and writes the reference data and the parity data to first and second memory blocks of the memory, respectively. The read access circuit receives the same address for a read operation associated with the memory and reads another reference data and another parity data from the first and second memory blocks, respectively. The fault management circuit compares the read parity data with parity data generated based on the read reference data to detect an address fault in the memory. The written and read reference data are different when the address fault is detected, and same when the address fault is not detected.

Abstract: One example discloses a signal driver circuit, including: an input configured to receive an input signal; an output configured to transmit an output signal; a low drop-out voltage regulator (LDO) having a regulated voltage output; a set of voltage-modulated amplifiers having a first input coupled to the regulated voltage output, and a second input configured to receive the input signal; wherein the voltage-modulated amplifier is configured to amplify the input signal and transmit an amplified input signal on the output of the signal driver circuit; a de-emphasis controller, including a set of de-emphasis levels; wherein the de-emphasis controller is configured to selectively switch-on a first subset of the set of voltage-modulated amplifiers and switch-off a second subset of the set of voltage-modulated amplifiers based on the de-emphasis levels.