Abstract: A combination of machine learning models is provided, according to certain aspects, by a data-aggregation circuit, and a computer server. The data-aggregation circuit is used to assimilate respective sets of output data from at least one of a plurality of circuits to create a new data set, the respective sets of output data being related in that each set of output data is in response to a common data set processed by the machine learning circuitry in the at least one of the plurality of circuits. The computer server uses the new data set to train machine learning operations in at least one of the plurality of circuits.

Abstract: Various embodiments relate to a method for multiplying a first and a second polynomial in a ring q [X]/(Xn+1) where q is a positive integer.

Abstract: An integrated electro-static discharge (ESD) device has a set of metal layers. Each metal layer in the set has one or more first-terminal metal features interleaved with one or more second-terminal metal features in a lateral direction, and at least one first-terminal metal feature in a metal layer of the set overlaps in a normal direction at least one second-terminal metal feature in an adjacent metal layer of the set. By overlapping metal features in the normal direction, capacitance can be added to the ESD device, which improves its operating characteristics, without increasing the layout size of the ESD device.

Abstract: Disclosed is a card clock recovery system for use in an NFC card transceiver couplable to an NFC reader.

Abstract: A method is provided for collecting diagnostic information in a device having a rich execution environment (REE) and a secure element (SE). The method includes detecting initialization of the device. If it is determined that the initialization of the device was a result of a potential security related event, a communication component of the REE responsible for communicating with the secure element is activated if not already activated. The secure element sends a request to the communication component for diagnostic information related to the security event. The diagnostic information is received in the SE from the communication component and stored in an attack log for storing security events. An attack log is generated in the secure element including the potential security event and the related diagnostic information. The attack log and the related diagnostic information is communicated to a secure server via a secure channel.

Abstract: Near field communication (NFC) methods, systems, and devices are disclosed herein. In an example embodiment, the method includes providing a first NFC device including a NFC antenna, and transmitting a radio frequency (RF) signal including a RF carrier signal by way of the NFC antenna. Also, the method includes receiving a first resonant signal after the transmitting has ceased, and processing the first resonant signal to generate a first portion of transformed signal information. Further, the method includes identifying one or both of a first state and a first event based at least in part upon or associated with the first portion of the transformed signal information.

Abstract: A mechanism is provided to secure integrated circuit devices that combines a high degree of security with a low overhead, both in area and cost, thereby making it appropriate for smaller, cheaper integrated circuits. A determination is made whether a device die is on a wafer or if the device die is incorporated into a package. Only if the device die is incorporated in a package can the functional logic of device die be activated, and then only if a challenge-response query is satisfied. In some embodiments, a random number generator is used during wafer testing to form a pair of numbers, along with a die identifier, that is unique for each device die. A final test is then performed in which the device die can be activated if the device die is incorporated in a package, and the die identifier—random number pair is authenticated.

Abstract: A Controller Area Network (CAN) transmitter, in which transitions between output levels are smoothed through use of multiple Digital to Analog Converters (DACs) switched by a multi-phase clock signal. Example embodiments include a CAN transmitter (100) comprising: an oscillator (101) configured to generate a clock signal having n equally spaced phases (clk_0, clk_120, clk_240), where n is an integer greater than 1; n Digital to Analog Converters, DACs (1021-3), each DAC having an input connected to one of the n phases of the clock signal and to a common data input line, each DAC being configured to provide an output signal that transitions between first and second output levels in M discrete steps upon being triggered by a transition of a signal on the data input line synchronized with the one of the n phases of the clock signal; and an output amplifier stage (103) configured to provide a differential CAN output signal from a combination of output signals from each of the n DACs (1021-3).

Abstract: An amplifier module includes a module substrate with a mounting surface, a signal conducting layer, a ground layer, and a ground terminal pad at the mounting surface. A thermal dissipation structure extends through the module substrate. A ground contact of a power transistor die is coupled to a surface of the thermal dissipation structure. Encapsulant material covers the mounting surface of the module substrate and the power transistor die, and a surface of the encapsulant material defines a contact surface of the amplifier module. A ground terminal is embedded within the encapsulant material. The ground terminal has a proximal end coupled to the ground terminal pad, and a distal end exposed at the contact surface. The ground terminal is electrically coupled to the ground contact of the power transistor die through the ground terminal pad, the ground layer of the module substrate, and the thermal dissipation structure.

Abstract: A transistor includes first and second sets of gate fingers formed in an active area of a semiconductor substrate, an input bond pad formed in the semiconductor substrate and spaced apart from the active area, a first conductive structure with a proximal end coupled to the input bond pad and a distal end coupled to the first set of gate fingers, and a second conductive structure with a proximal end coupled to the input bond pad and a distal end coupled to the second set of gate fingers. A non-conductive gap is present between the distal ends of the first and second conductive structures. The transistor further includes an odd-mode oscillation stabilization circuit that includes a first resistor with a first terminal coupled to the distal end of the first conductive structure, and a second terminal coupled to the distal end of the second conductive structure.

Abstract: Systems and methods for preserving a decoupling capacitor's charge during low power operation of a logic circuit. An electronic circuit may include: a main voltage regulator coupled to a supply voltage terminal and configured to apply a first regulated voltage across a capacitor coupled in parallel with a logic circuit; a low power regulator coupled to the supply voltage terminal and configured to apply a second regulated voltage across the logic circuit; and a control circuit coupled to the low power regulator. The control circuit may be configured to: during a first mode of operation, allow the main voltage regulator to apply the first regulated voltage to the logic circuit, and, during a second mode of operation, allow the low power regulator to apply the second regulated voltage to the logic circuit and decouple the capacitor from the logic circuit while the low power regulator applies the second regulator voltage.

Abstract: Various embodiments relate to a method for a non simultaneous transmit and receive (NSTR) soft access point (AP) multi-link device (MLD) negotiating a traffic identifier (TID)-to-link mapping with a non-AP MLD, including: transmitting, by the NSTR soft AP MLD, a first frame that includes information on a first group of links that the NSTR soft AP MLD proposes to map to a first TID for the non-AP MLD; receiving, by the NSTR soft AP MLD, a second frame that includes an indication that the non-AP MLD agrees with the NSTR soft AP MLD's proposal on mapping of the first TID to the first group of links; and transmitting, by the NSTR soft AP MLD, traffic to the non-AP MLD on the first group of links based on the mapping.

Abstract: A microprocessor system includes a processing circuit and a memory operably coupled to the processing circuit and configured to receive input data according to a pack and store operation and output the data according to a load and unpack operation. The processing circuit comprises a hardware extension configured to: configure a variable number of bits per data element during a pack and store operation; store a concatenation of a plurality of data elements with a reduced number of bits; extract a plurality of data elements with a reduced number of bits during a load and unpacking operation; and recreate a plurality of data elements with an increased number of bits per data element representative of the data elements prior to the pack and store operation.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming an assembly including placing a semiconductor die and a launcher structure on a carrier substrate, encapsulating at least a portion of the semiconductor die and the launcher structure, and applying a redistribution layer on a surface of the semiconductor die and a surface of the launcher structure to connect a bond pad of the semiconductor die with an antenna launcher of the launcher structure. The assembly is attached to a substrate and a waveguide overlapping the assembly is attached to the substrate. The waveguide structure is physically decoupled from the assembly.

Abstract: Embodiments of a method and an apparatus for wireless operations are disclosed. In an embodiment, a method for wireless operations involves a first wireless device transmitting to a second wireless device, a management frame having a multi-link device (MLD) level Quality of Service Management Frame (QMF) Policy field that identifies an MLD level QMF Policy and a link level QMF Policy field that identifies a link level QMF Policy for a corresponding link, where the MLD level QMF Policy indicates an Access Category (AC) for each MLD level QMF management frame and each link level QMF Policy field indicates the AC for each link level QMF management frame, receiving, at the second wireless device, the management frame with the MLD level QMF Policy field and link level QMF Policy field for each corresponding link, and operating the second wireless device according to the AC indicated by the first wireless device.

Abstract: Embodiments of a method and apparatus for communications are disclosed. In an embodiment, a method for wireless communications involves, in a punctured transmission, encoding, bits in a non-legacy preamble portion of a packet to include bandwidth information and resource allocation information, and signaling, in the packet, the bandwidth information and resource allocation information for at least one of a single-user-multiple-input multiple-output (SU-MIMO) technique, a multiple-user-multiple-input multiple-output (MU-MIMO) technique, and an orthogonal frequency-division multiple access (OFDMA) technique.

Abstract: A device assembly includes a functional substrate having one or more electronic components formed there. The functional substrate has a cavity extending from a first surface toward a second surface of the functional substrate at a location that lacks the electronic components. The device assembly further includes a semiconductor die placed within the cavity with a pad surface of the semiconductor die being opposite to a bottom of the cavity. The functional substrate may be formed utilizing a first fabrication technology and the semiconductor die may be formed utilizing a second fabrication technology that differs from the first fabrication technology.

Abstract: A method and system are provided for supplying power to a backup power domain by connecting a battery voltage to a supply terminal for a backup power domain in a low power microcontroller during a startup mode when a main supply voltage, by detecting application of the main supply voltage to the low power microcontroller at a predetermined safe voltage level, and by activating a selection control circuit to power the backup power domain in the low power microcontroller from the main power supply voltage or the backup power supply voltage based on a software-controlled configuration bit, where the selection control circuit is configured to connect, in response to the software-controlled configuration bit having a first user-selected value, the main power supply voltage to the supply terminal for the backup power domain when the main power supply voltage is smaller than the battery power supply voltage.

Abstract: A method for in situ threshold voltage determination of a semiconductor device includes sourcing a current to a first terminal of the semiconductor device. A gate terminal of the semiconductor device is driven with a plurality of gate levels. Each gate level includes one of a plurality of different gate voltages. A transistor voltage is measured between the first terminal and a second terminal of the semiconductor device during each gate level. The respective gate voltage is stored in response to the semiconductor device voltage transitioning past a voltage limit. A temperature dependent threshold voltage of the semiconductor device is estimated for a first measured temperature measured during the storing of the stored gate voltage from a previously stored gate voltage and a second measure temperature.

Abstract: Testing clock division circuitry includes generating pseudo random test pattern bits for scan chain logic in programmable clock division logic circuitry and divided clock counter circuitry. A shift clock is used to shift the test pattern bits into the scan chain logic. A capture clock signal is used in the programmable clock division logic during a non-test mode of operation. The shift clock is used to provide output shift bits from the scan chain logic to a multi-input shift register (MISR). Once all the output shift bits for the test pattern bits are provided to the MISR, a final test signature from the MISR is compared to an expected test signature to determine whether the programmable clock division logic circuitry and divided clock counter circuitry are free of faults.