Abstract: There is disclosed an audio playback system including a loudspeaker, a microphone and a means for implementing a method of detecting a fault which includes the generation and analysis of a specific ultrasound reference signal. The presence of the ultrasound reference signal can be detected on the microphone signal, and the signal-to-noise ratio can be estimated during the reference signal playback so that the volume of the reference signal can be adapted if necessary. The reference signal is a multi-sinusoidal signal which, when averaged over time increases the expected signal-to-noise ratio, and hence, the power of the detector.

Abstract: A controller for a half-bridge power circuit includes a measurement circuit, a controller circuit, a high-side delay circuit, and a low-side delay circuit. The measurement circuit connects to the half-bridge node, measures the half-bridge voltage, and generates a multi-bit status signal indicative of the measured half-bridge voltage. The controller circuit connects to the measurement circuit, and receives the status signal therefrom. The controller circuit generates at least a delay control signal based on the status signal. The high-side delay circuit connects to the controller circuit to receive the delay control signal. The high-side delay circuit provides a high-side control signal in response to the delay control signal, to switch on/off the high-side switch. The low-side delay circuit connects to the controller circuit to receive the delay control signal. The low-side delay circuit provides a low-side control signal in response to the delay control signal, to switch on/off the low-side switch.

Abstract: A technique for handling an integrated circuit/tape assembly having a plurality of integrated circuits supported by underlying dicing tape involves placing the integrated circuit/tape assembly on a bottom file frame carrier (FFC) frame having structure (e.g., an inner rim or flexible pegs), placing a top FFC frame having a central opening over the integrated circuit/tape assembly, and mating the top and bottom FFC frames such that the dicing tape is pulled over the structure thereby laterally stretching the dicing tape, which breaks wafer saw bows holding the integrated circuits together. The lateral stretching of the dicing tape increases distance between adjacent integrated circuits in at least two mutually orthogonal lateral directions, thereby inhibiting the adjacent integrated circuits from colliding during shipment or storage for subsequent processing. The resulting assembly can be thinner than conventional FFC configurations, which results in more efficient shipment and storage.

Abstract: An integrated circuit (IC) includes a clocking system that generates first and second clock signals and a clock enable signal, and a testing system that tests the clocking system. During a capture phase of an at-speed testing mode of the IC, the second clock signal is a gated version of the first clock signal and includes two clock pulses. The testing system determines a first count of clock pulses of the first clock signal between an activation of the capture phase and an assertion of the clock enable signal. Similarly, the testing system determines a second count of clock pulses of the first clock signal between the two clock pulses of the second clock signal. The testing system then compares the first count with a first reference value and the second count with a second reference value to detect a fault in the clocking system.

Abstract: In one example, a continuous-wave radar circuit receives reflection signals, computer processing circuitry processes data corresponding to the reflection signals, and emulation circuitry introduces a plurality of diagnostic data sets into the radar circuit to cause the radar circuit to process simulated reflection signals as though the simulated reflection signals are reflections from objects remote from the apparatus. The radar circuit may receive the reflection signals in response to chirp sequences actually transmitted as reflections from objects.

Abstract: Embodiments of a method and an apparatus for wireless communications are disclosed. In an embodiment, a method for wireless communications involves encoding bits in a Physical Layer Protocol Data Unit (PPDU) using a basic bandwidth that is smaller than a signal bandwidth, wherein the bits are duplicated within the PPDU, and transmitting the PPDU with duplicated bits in accordance with a power spectrum density (PSD) limit.

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts n partitions by accessing, for each partition, one or more SoC resources; a control point processor that generates control data with n JTAG debug enable signals corresponding to the n partitions for controlling access to the SoC resources by identifying at least a first SoC resource that each partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which allows access by the JTAG debugging tool to only a specified partition running on the execution domain which has a JTAG debug enable signal set to a first active value and prevents access to the other n-1 partitions running on the execution domain, and for the partition under debug (debug signal set to a first active value), the dynamic runtime isolat

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain; a control point processor that is physically and programmatically independent from the execution domain processor and configured to generate control data for controlling access by the execution domain to one or more SoC resources by identifying at least a first SoC resource that the execution domain is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and including a programmable front end which is connected to receive the control data from the control point processor, and a signals-based back end which is configured to provide a dynamic runtime isolation barrier in response to the control data, thereby controlling access to the one or more system-on-chip resources by the execution domain.

Abstract: A method and apparatus are disclosed for a multi-processor SoC which includes an execution domain processor for running an execution domain which hosts independent software partitions by accessing, for each software partition, one or more SoC resources; a control point processor that generates control data with pre-emption vectors for controlling access to the SoC resources by identifying at least a first SoC resource that each software partition is allowed to access; and an access control circuit connected between the execution domain and the SoC resources and configured to provide, in response to the control data, a dynamic runtime isolation barrier which enables the execution domain processor to switch between software partitions in response to a pre-emption interrupt trigger by fetching partition instructions from a corresponding pre-emption interrupt vector address in memory that is associated with the pre-emption interrupt trigger.

Abstract: A method and apparatus are disclosed for a multi-processor system on a chip which includes at least a first execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip (SoC) resources using virtual addresses; a control point processor that is physically and programmatically independent from the first execution domain processor and that is configured to generate a runtime virtualization isolation control data stream for controlling access to the SoC resources by identifying at least a first SoC resource that the first execution domain is allowed to access; and an access control circuit connected between the first execution domain and the SoC resources and configured to provide, in response to the runtime virtualization isolation control data stream, a dynamic runtime virtualization isolation barrier which maps a virtual address for the first SoC resource to a physical address for the first SoC resource.

Abstract: A method and apparatus are disclosed for a multi-processor system on a chip which includes at least a first execution domain processor that is configured to run a first execution domain by accessing one or more system-on-chip resources; a first control point processor that is physically and programmatically independent from the first execution domain processor and that is configured to generate a first runtime isolation control data stream for controlling access to the one or more system-on-chip resources by the first execution domain; and an access control circuit connected between the first execution domain processor and the one or more system-on-chip resources and configured to provide a dynamic runtime isolation barrier in response to the first runtime isolation control data stream, thereby controlling access to the one or more system-on-chip resources by the first execution domain.

Abstract: In accordance with a first aspect of the present disclosure, a radio frequency identification (RFID) transponder is provided, comprising: a receiver configured to receive a command from an external RFID reader, wherein the command is a first command transmitted by the RFID reader during a communication session and wherein said command comprises a at least one parameter indicative of one or more modifiable settings of the RFID transponder; and a controller configured to modify the settings of the RFID transponder in accordance with a value of said parameter. In accordance with a second aspect of the present disclosure, a corresponding method of operating a radio frequency identification (RFID) transponder is conceived.

Abstract: In accordance with a first aspect of the present disclosure, a method is conceived for determining the position of at least one node in a communication network, wherein the communication network comprises a localization system that includes a processing unit, a primary anchor and at least one secondary anchor, the method comprising: the primary anchor transmits a poll message to the node and to the secondary anchor; the primary anchor receives a response message from the node; the secondary anchor receives said poll message from the primary anchor and said response message from the node; the processing unit calculates the position of the node using position information and timing information, wherein said position information is position information of the primary anchor and of the secondary anchor, and wherein said timing information is timing information of the poll message transmission by the primary anchor, of the poll message reception by the node and the secondary anchor, of the response message transmi

Abstract: Cut-through frame transfer or store-and-forward frame transfer of a frame in an network switch is disclosed. A frame is received from an input port of the switch. A time period in a cycle time when the frame is received and a stream identification of the frame is determined. One of the cut-through frame transfer and the store-and-forward frame transfer of the frame is performed based on the time period in the cycle time when the frame was received and the stream identification.

Abstract: An electronic component includes a device die and a substrate. The device die includes conductive contacts with conductive pillars conductively affixed to conductive contact. The conductive pillars include a cavity formed in an end of the conductive pillar opposite the conductive contact. The substrate includes of conductive pads that are each associated with one of the conductive contacts. The conductive pads include a conductive pad conductively affixed to the substrate, and a conductive ring situated within a cavity in the end conductive rings have a capillary formed along an axis of the conductive ring. A solder material fills the capillary of each of the conductive rings and the cavity formed in the end of the associated conductive pillars to form a conductive joint between the pillars and the conductive pads.

Abstract: An infrastructure-controller for an infrastructure. The infrastructure-controller configured to: send a ranging-scheduling-signal to a key, wherein the ranging-scheduling-signal comprises timing-information for a subsequent ranging operation; and activate one or more ranging nodes associated with the infrastructure, for receiving a key-ranging-signal from the key, at an infrastructure-node-start-ranging-time based on the timing-information. The ranging-scheduling-signal has a frequency in a first RF frequency range. The key-ranging-signal has a frequency in a second RF frequency range.

Abstract: There is described a hybrid ADC device for converting an analog input signal (Vin) into a digital output signal (Vout), the device comprising a first ADC circuit configured to receive the analog input signal (Vin) and convert it into a first digital signal (Y0); a DAC circuit configured to receive the first digital signal and convert it into a first analog signal; a delay circuit configured to delay the analog input signal; a first combiner configured to generate an analog residual signal by subtracting the first analog signal from the delayed analog input signal; a second ADC circuit configured to receive the residual analog signal and convert it into a second digital signal (Y1); a filter circuit configured to receive the first digital signal and output a filtered first digital signal (Y0?), the filter circuit having a transfer function corresponding to a combined transfer function of the DAC circuit and the second ADC circuit; and a second combiner configured to generate the digital output signal (Vout) by

Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain stage circuit having a first gain stage input coupled at a first oscillator terminal and configured to receive a first oscillator signal of a crystal. A first bias circuit is configured to generate a first bias voltage based on the first oscillator signal. A reference circuit is configured to generate a reference current based on the first bias voltage. A comparator circuit is configured to generate a clock signal based on the first oscillator signal and the first bias voltage. The comparator circuit includes a second bias circuit configured to generate a second bias voltage. The gain stage circuit includes a second gain stage input coupled to receive the second bias voltage.

Abstract: A semiconductor device having a radiating element and a directing structure is provided. The semiconductor device includes a device package. A semiconductor die is coupled to the radiating element integrated in the device package. The directing structure is affixed to the device package by way of an adhesive. The directing structure is located over the radiating element and configured for propagation of radio frequency (RF) signals.

Abstract: An apparatus and method for updating the firmware version in a network node is described. The firmware is divided into a plurality of blobs, each blob having an associated blob version. Each blob version is associated with a firmware version. The method includes receiving notification from a client server network node of an updated version of a first blob and the compatible versions of the remaining blobs. A blob upgrade order is determined from the first blob updated version, the remaining blobs compatible versions, and the remaining blobs current versions. Each blob is upgraded in the blob upgrade order. The client is restarted after each blob upgrade.