Abstract: An error amplifier circuit for a DC-DC power converter controller is disclosed for providing an amplified error signal to a switch control circuit, the circuit comprising an error amplifier first stage. The first stage comprises: a first input terminal for receiving a voltage proportional to an output voltage of the converter; an output node; a first operational transconductance amplifier in a first path between the input terminal and the output node and having a first input connected to the input terminal, a second input connectable to a reference signal, and an output connected to the output node; and a second, parallel, path comprising a series combination of an amplifier, a second OTA and a capacitor. The second OTA has an output connected to the capacitor, a first input connected to an output of the amplifier, and a second input connected to the output. Associated control circuits, controllers and converters are also disclosed.

Abstract: A semiconductor device package having stress isolation is provided. The semiconductor device package includes a package substrate and a sensor attached to the package substrate. A first isolation material is formed around a perimeter of the sensor. An encapsulant encapsulates at least a portion of the first isolation material and the package substrate.

Abstract: A wireless power transmitter to wirelessly transmit power applies a current or voltage to a transmitter coil based on an indication of coupling being in a predetermined range. The current or voltage which is applied causes the transmitter coil to transmit a high power (HP) DPING. A response to the HP DPING indicates that a wireless power receiver is located on a charging surface and a power signal is then transmitted to the wireless power receiver to charge or power an electronic device coupled to the wireless power receiver. Use of HP DPING improves the wireless power transmission performance including transmission area and interoperability of wireless power transmitters with low coupling to wireless power receivers.

Abstract: A method is provided for estimating a signal's angle of arrival (AOA) in a communications system. Starting values for each of a horizontal AOA and a vertical AOA are estimated. The estimated vertical AOA starting value is used to select a horizontal PDOA trace of horizontal PDOA calibration data. The selected horizontal PDOA trace is interpolated to determine a best horizontal AOA estimate for a current iteration. The estimated horizontal AOA starting value is used to select a vertical PDOA trace of vertical PDOA calibration data. The selected vertical PDOA trace is interpolated to determine a best vertical AOA estimate for the current iteration. After each iteration, determining if a maximum number of iterations has been reached or if the best horizontal or vertical AOA estimate has not changed by a predetermined amount. When one of these is true, the best horizontal and vertical AOA estimates are used.

Abstract: An integrated circuit comprises a substrate that includes a first surface and a second surface. A first through substrate via (TSV) is formed between the first surface and the second surface and a first conductive material is arranged within the first TSV to form a conductive path between the first surface and the second surface through the substrate. A second TSV is formed between the first surface and the second surface and a second conductive material arranged within the second TSV to form a conductive path between the first surface and the second surface through the substrate. In examples the first TSV has a larger cross-sectional area than the second TSV, the cross-section of the first TSV and second TSV being in a plane parallel to the first surface or the second surface.

Abstract: Aspects of the present disclosure are directed toward apparatuses and/or methods involving the communication of radar signals. Certain aspects involve communicating time division multiplexing (TDM) multi-input multi-output (MIMO) radar signals, having pulses with a chirp interval time (CIT) that is different for respective chirps. Positional characteristics of a target may be ascertained based upon both the CIT between each chirp in the communicated radar signals and the time between each corresponding chirp in received ones of the signals reflected by the target. Communication of the radar signals may involve utilizing a combination of antennas to provide a virtual aperture.

Abstract: A receiver comprising: a processing module configured to: receive a first portion of a packet of received signalling from a first antenna; receive a carrier estimate signal; adjust the first portion based on the carrier estimate signal and correlate the signal with an expected code sequence to provide a first correlated signal; a tracking module configured to: receive the first correlated signal and update the carrier estimate signal, wherein the processing module is further configured to: receive a second portion of the packet from a second antenna; adjust the second portion based on the carrier estimate signal and correlate the signal to provide a second correlated signal, and wherein the receive path further comprises a phase calculation module configured to: receive the first and second correlated signals and determine a respective first and second carrier phase and an angle of arrival of the received signalling.

Abstract: The disclosure relates to apparatus and methods for self-testing of a duty cycle detector. Example embodiments include a circuit (201) comprising: a clock signal generator (205) configured to provide an output clock signal (203) having a duty cycle; a duty cycle detector (208) arranged to receive the output clock signal (203) and provide an output flag if the duty cycle of the clock signal (203) is outside a predetermined range; a controller (214) arranged to provide a duty cycle select signal (216) to the clock signal generator (205) to cause the clock signal (203) to have a duty cycle outside the predetermined range and to receive the output flag to confirm operation of the duty cycle detector (208).

Abstract: One example discloses a switch mode power supply (SMPS) circuit configured to receive an input voltage and generate an output voltage, including: a set of switching devices configured to receive the input voltage; a first transformer, having an input winding coupled to the switching devices, and an output winding configured to generate the output voltage; a second transformer, having an input winding coupled to receive the output voltage from the first transformer, and an output winding configured to generate an output voltage monitoring signal; and a controller configured to control the switching devices based on the output voltage monitoring signal.

Abstract: A semiconductor device and a method of making a semiconductor device are described. The device includes an emitter. The device also includes a collector. The device further includes a base stack. The base is located between the emitter and the collector. The base stack includes an intrinsic base region. The device further includes a base electrode. The base electrode comprises a silicide. The silicide of the base electrode may be in direct contact with the base stack. The device may be a heterojunction bipolar transistor.

Abstract: A sequence recovery method executed by a node in a time-sensitive network, the method comprising receiving a packet having a sequence number, determining whether the sequence number is within a predetermined range of a reference sequence number, wherein the reference sequence number is a current latest sequence number accepted by the node, and wherein the predetermined range comprises a history range and a future range, wherein the history range has a length equal to a history length and includes the reference sequence number and a predetermined number of consecutive sequence numbers that are immediately earlier than the reference sequence number, and the future range has a length equal to a future length and defines a predetermined number of consecutive sequence numbers that are immediately later than the reference sequence number, wherein the future length is greater than the history length.

Abstract: In imaging radar, examples are directed to uses of multiple sets of transmit antenna included with transceiver circuitry, for transmitting in a plurality of modes. Transmissions may involve having at least one transmit antenna, from each of at least two of the multiple sets, to transmit continuous-wave energy concurrently (simultaneously) in one or more of the plurality of different modes. Transceiver circuitry may include multiple receive antennas which may be receiving reflections of the continuous-wave energy from various targets. Signals from the multiple receive antennas may route to signal processing circuitry. The signal processing circuitry may respond to the received reflections of the continuous-wave energy by assessing differences in antenna gain and/or phase due to transmit antenna position associated with the received reflections.

Abstract: A semiconductor device package having a thermal dissipation feature is provided. The semiconductor device package includes a package substrate. A semiconductor die is mounted on a first surface of the package substrate. A first conductive connector is affixed to a first connector pad of the package substrate. A conformal thermal conductive layer is applied on the semiconductor die and a portion of the first surface of the package substrate. The conformal thermal conductive layer is configured and arranged as a thermal conduction path between the semiconductor die and the first conductive connector.

Abstract: A digitally modulated radar, DMR, transmitter module is disclosed comprising: a sequence generator, configured to generate a repeating digital sequence signal based on a relatively low-frequency clock signal; a mixer configured to combine the digital sequence signal with at least one phase-delayed copy of the digital sequence signal, to provide a combined signal; and a modulator configured to modulate a relatively high-frequency carrier signal, in dependence on the combined signal, to provide a modulated signal. Corresponding systems and methods are also disclosed.

Abstract: A control system for a digitally controlled oscillator with temperature compensation including a loop detector providing an error value, filter circuitry providing a lower resolution digital value to the DCO to generate an output oscillation signal at a frequency within a lower resolution range, tracking circuitry holding a tracking digital value at a tracking offset from center of a tracking range while the lower resolution digital value is being determined, and then regulating the frequency within a higher resolution range by adjusting the tracking digital value, temperature compensation circuitry performing temperature compensation steps to maintain the tracking digital value between first and second thresholds within the predetermined tracking range, and a controller configured to set the first and second thresholds within a narrow range around the tracking offset during a standard operating mode, and to adjust one or both thresholds within a wide range during a critical operating mode.

Abstract: A hardware multithreaded processor including a register file, a thread controller, and aliasing circuitry. The thread controller is configured to assign each of multiple hardware processing threads to a corresponding one of multiple register block sets in which each register block set includes at least two of multiple register blocks and in which each register block includes at least two registers. The aliasing circuitry is programmable to redirect a reference provided by a first hardware processing thread to a register of a register block assigned to a second hardware processing thread. The reference may be a register number in an instruction issued by the first hardware processing thread. The register number is converted by the aliasing circuitry to a register file address locating a register of the register block assigned to the second hardware processing thread. The aliasing circuitry may include a programmable register for one or more threads.

Abstract: A method and system are provided to resolve Doppler ambiguity and multiple-input, multiple-output array phase compensation issues present in Time Division Multiplexing MIMO radars by estimating an unambiguous radial velocity measurement. Embodiments apply a disambiguation algorithm that dealiases the Doppler spectrum to resolve the Doppler ambiguity of a range-Doppler detection. Phase compensation is then applied for corrected reconstruction of the MIMO array measurements. The dealiasing processing first forms multiple hypotheses associated with the phase corrections for the radar transmitters based on a measured radial velocity of a range-Doppler cell being processed. A correct hypothesis, from the multiple hypotheses, is selected based on a least-spurious spectrum criterion. Using this approach, embodiments require only single-frame processing and can be applied to two or more transmitters in a TDM MIMO radar system.

Abstract: The disclosure relates to a communications system having a transmitter and receiver connected via a transmission line. An example communications receiver (202) comprises: a pair of input connections (211, 212) for connecting to a transmission line (203); a termination resistance (213) equal to a characteristic impedance (Zc) of the transmission line (203); an air core transformer (205) having an input coil (206) connected to the pair of input connections (211, 212) via the termination resistance (213); and a comparator circuit (208) connected to an output coil (207) of the air core transformer (205), the comparator circuit (208) configured to provide an output signal (504) responsive to detection of voltage pulses across the output coil (207).

Abstract: A packaged integrated circuit (IC) includes an IC die having first and second external contacts and a package substrate. The IC die is attached to the package substrate which includes a balun in a first metal layer. The balun is connected to the first and second external contacts of the IC die and to a first external contact of the package substrate. The first and second external contacts of the IC die communicate a differential signal with the package substrate, and the first external contact of the package substrate communicates a single-ended signal corresponding to the differential signal. Alternatively, the balun is connected to an external contact of the IC die and to first and second external contacts of the package substrate, in which the external contact of the IC die communicates a single-ended signal and the first and second external contacts of the package substrate communicate a differential signal.

Abstract: A method is provided for identifying or authenticating an object. The method includes vibrating the object at a plurality of frequencies. The vibrations from the object are sensed at each of the plurality of frequencies using an accelerometer. A vibration profile of the object is generated using the sensed vibrations. The generated vibration profile is then compared to a stored vibration profile. It is determined if the generated vibration profile matches the stored vibration profile. A match indicates that the object has been identified or authenticated. In another embodiment, an object capable of implementing the method is provided. In another embodiment, the object may include a replaceable accessary. In this case, the initial and generated vibration profiles may be created with the replacement accessary attached to the object. A match of the generated and initial vibration profiles indicates that the replaceable accessary is authentic.