Patents Assigned to NXP
  • Patent number: 11812274
    Abstract: There is described a system and method of committing a transaction within a UWB network comprising a plurality of anchors, the UWB network covering a predetermined area having at least one trigger area, the method comprising waking up a mobile device upon entering the predetermined area, receiving initial network data at the mobile device, verifying that the UWB network is genuine based on the initial network data, initiating communication between the mobile device and an anchor, including partial mutual authentication, generating a session key for secure communication between the mobile device and the UWB network, tracking the location of the mobile device within the predetermined area based on secure communication between the mobile device and one or more anchors within the UWB network using the session key, and committing the transaction, if the location of the mobile device is within the at least one trigger area.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: November 7, 2023
    Assignee: NXP B.V.
    Inventors: Hugues Jean Marie de Perthuis, Frank Leong, Sören Heisrath, Srivathsa Masthi Parthasarathi
  • Patent number: 11809531
    Abstract: A method is provided for watermarking a machine learning model. In the method, a first subset of a labeled set of ML training samples is selected. The first subset is of a predetermined class of images. A first pixel pattern is selected and inserted into each sample of the first subset. One or more of a location, position, orientation, and transformation of the first pixel pattern is varied for each of the samples. Each sample of the first subset is relabeled to have a different label than the original label. The ML model is trained with the labeled set of ML training samples and the first subset of relabeled ML training samples. To detect the watermark, a second subset of training samples is selected, and the first pixel pattern is inserted into each sample. The second subset is used during inference operation to detect the presence of the watermark.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 7, 2023
    Assignee: NXP B.V.
    Inventor: Wilhelmus Petrus Adrianus Johannus Michiels
  • Patent number: 11811317
    Abstract: A controller for controlling a DC-DC converter in a discontinuous conduction mode (DCM) includes an output module configured to provide a switch control signal to the DC-DC converter having an on-time and a switching frequency. The controller includes an on-time-control-module configured to receive a first compensation signal based on the output voltage of the DC-DC converter; and set the on-time of the switch control signal based on the first compensation signal. The controller also includes a frequency-control-module configured to receive a second compensation signal, wherein the second compensation signal is based on the output voltage of the DC-DC converter, and regulate the second compensation signal to a target range by setting the switching frequency of the switch control signal to one of a plurality of pre-defined discrete switching frequencies.
    Type: Grant
    Filed: May 20, 2021
    Date of Patent: November 7, 2023
    Assignee: NXP B.V.
    Inventors: Ravichandra Karadi, Matthias Rose, Hendrik Johannes Bergveld, Marcel Dijkstra
  • Patent number: 11811245
    Abstract: A method of compensating for temperature dependent Q factor variations in a wireless charger includes receiving, by the wireless charger, a reference Q factor value from a device to be charged. The method also includes the wireless charger determining a Q factor threshold value from the reference Q factor. The method further includes the wireless charger measuring a Q factor associated with a transmit coil of the wireless charger. The method also includes determining a temperature value. The method further includes applying a temperature compensation calculation to the measured Q factor using the temperature value to produce a temperature compensated Q factor. The method also includes comparing the temperature compensated Q factor with the Q factor threshold value. The method may also include compensation for temperature dependent internal power loss values.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: November 7, 2023
    Assignee: NXP USA, Inc.
    Inventors: Huan Mao, Dechang Wang, Dengyu Jiang
  • Patent number: 11808804
    Abstract: An integrated circuit (IC) includes subcircuits, power switches coupled to pass load current to a respective one of the subcircuits when activated by a respective switch control signal, and sensing circuits. Each of the sensing circuits is coupled to a respective one of the subcircuits, wherein the sensing circuits are configured to generate sense currents that are proportional to the respective load currents. The IC also includes a conversion circuit configured to receive at least one of the sense currents and to convert the at least one of the sense currents to an equivalent multi-bit digital signal, a timestamp circuit configured to generate a timestamp value that is correlated with the multi-bit digital signal, and a controller configured to provide signals to operate the power switches and the sensing circuits.
    Type: Grant
    Filed: December 15, 2020
    Date of Patent: November 7, 2023
    Assignee: NXP USA, Inc.
    Inventors: Antonio Mauricio Brochi, Felipe Ricardo Clayton
  • Patent number: 11805470
    Abstract: A reduced neighbor report (RNR) element is generated. The generated RNR element includes multi-link device operation (MLO) information of least one neighboring wireless device to a reporting wireless device. In examples, the MLO information defines information of a respective multi-link device (MLD) which each at least one neighboring wireless device to the reporting wireless device is affiliated. A multilink (ML) element is also generated. The generated ML element includes basic service set (BSS) information of each of at least one wireless device affiliated to an MLD where the reporting wireless device is affiliated to the same MLD. The reporting wireless device transmits a frame which comprises the generated RNR element and the generated ML element, where the generated ML element does not include any other RNR element.
    Type: Grant
    Filed: May 16, 2021
    Date of Patent: October 31, 2023
    Assignee: NXP USA, Inc.
    Inventors: Young Hoon Kwon, Liwen Chu, Hongyuan Zhang
  • Patent number: 11803324
    Abstract: A transaction management system includes a storage circuit and a processing circuit. The storage circuit stores a current tag value of a tag ID of a device and a tag value associated with a transaction initiated by the device. The processing circuit receives a reset query to determine an availability of the device for reset. When the device is to be reset, the current tag value of the tag ID is updated. Further, the processing circuit generates an acknowledgment in response to the reset query such that the device is reset based on the acknowledgment. The updated tag ID ensures that responses for transactions that are initiated by the device before the reset are discarded.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: October 31, 2023
    Assignee: NXP B.V.
    Inventors: Arvind Kaushik, Nishant Jain
  • Patent number: 11804911
    Abstract: A measurement apparatus comprising a first terminal to receive an input signal of a circuit under test; a second terminal to receive an output signal of the circuit under test. A first and second phase splitter configured to generate a first and second phase signal, I1 and I2, and a first and second quadrature signal, Q1 and Q2. A first and second multiplexer, each coupled to the first terminal and the second terminal and configured to alternately pass the input and output signals of the circuit under test to the inputs of the first and second phase splitters. A double-quadrature mixer having four inputs configured to receive I1, Q1, I2, and Q2, and an output. A calculation unit to determine one or both of a phase shift of the circuit under test and/or a gain of the circuit under test based on the output of the double-quadrature mixer.
    Type: Grant
    Filed: July 12, 2022
    Date of Patent: October 31, 2023
    Assignee: NXP B.V.
    Inventors: Frank Op 't Eynde, Olivier Crand, Milad Piri
  • Patent number: 11804709
    Abstract: An ESD protection circuit that includes a clamp path including two clamp transistors and a GIDL detection circuit for detecting GIDL current conditions in the ESD protection circuit. The GIDL detection circuit generates a signal indicative of a GIDL current condition. The signal is utilized to control a voltage of a control electrode of a clamp transistor of the clamp path to increase the conductivity of the clamp transistor when the signal is indicative of a GIDL current condition to minimize a GIDL current through at least through a portion of the clamp path when the second clamp transistor is nonconductive where no ESD current is being discharged through the clamp path.
    Type: Grant
    Filed: October 29, 2021
    Date of Patent: October 31, 2023
    Assignee: NXP B.V.
    Inventors: Marcin Grad, Chinmayee Kumari Panigrahi, Maciej Skrobacki
  • Patent number: 11804527
    Abstract: A transistor includes a source contact connected to a Through-Silicon Via (TSV). A drain contact is connected to a first pad. A gate structure is interposed between the source contact and the drain contact. A second pad is connected to the gate structure, the second pad comprising a first side diametrically opposed to a second side, and a third side interposed therebetween, the source contact proximal to the third side, a first portion of the first side and a second portion of the second side.
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: October 31, 2023
    Assignee: NXP USA, Inc.
    Inventors: Vikas Shilimkar, Kevin Kim, Daniel Joseph Lamey, Bruce McRae Green, Ibrahim Khalil, Humayun Kabir
  • Publication number: 20230343749
    Abstract: Semiconductor packages with embedded wiring on re-distributed bumps are described. In an illustrative, non-limiting embodiment, a semiconductor package may include an integrated circuit (IC) having a plurality of pads and a re-distribution layer (RDL) coupled to the IC without any substrate or lead frame therebetween, where the RDL comprises a plurality of terminals, and where one or more of the plurality of pads are wire bonded to a corresponding one or more of the plurality of terminals.
    Type: Application
    Filed: April 25, 2022
    Publication date: October 26, 2023
    Applicant: NXP B.V.
    Inventors: Kuan-Hsiang Mao, Norazham Mohd Sukemi, Chin Teck Siong, Tsung Nan Lo, Wen Hung Huang
  • Publication number: 20230345623
    Abstract: A packaging assembly and methodology provide a PCB substrate with one or more waveguide apertures and a conductive pattern which includes a plurality of landing pads that are disposed around peripheral edges of each waveguide aperture and that are connected to one another by trace lines so that, upon attachment and reflow of solder balls to the plurality of landing pads, the solder balls reflow along the trace lines to form a fully closed solder waveguide shielding wall disposed around peripheral edges of the first waveguide aperture.
    Type: Application
    Filed: April 21, 2022
    Publication date: October 26, 2023
    Applicant: NXP B.V.
    Inventors: Leo van Gemert, Michael B. Vincent
  • Patent number: 11800445
    Abstract: Aspects of the present disclosure are directed to wireless communications based on a restricted TWT SP and buffer status. As may be implemented in accordance with one or more embodiments, frames are transmitted based on a restricted TWT SP and buffer status for communications between wireless circuits. Control data for the communications traffic may be processed in response to the restricted TWT SP, with a TXOP ending at the beginning of a restricted TWT SP of a another link, in response to the restricted TWT SP being negotiated in a different link. Such an approach may be carried out where one of the wireless circuits has no STR configuration. A protected duration time for the TWT SP may be set to a time that is less than a duration of the TWT SP in response to the TWT SP being protected by a quiet element duration period.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: October 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Liwen Chu, Young Hoon Kwon, Hongyuan Zhang, Huiling Lou
  • Patent number: 11796632
    Abstract: A radar system utilizing a linear chirp that can achieve a larger MIMO virtual array than traditional systems is provided. Transmit channels transmit distinct chirp signals in an overlapped fashion such that the pulse repetition interval is kept short and the frame is kept short. This alleviates range migration and aids in achieving a high frame update rate. The chirp signals from differing transmitters can be separated on receive in the range spectrum domain, such that a MIMO virtual array construction is possible. Distinct chirps are delayed versions of the first chirp signal. Chirps overlap in the fast-time domain, but due to delay, there is separation in the range spectrum domain. When the delay is at least the instrument round-trip delay, transmitters are separable. Further, the wavelengths are identical across transmitters such that there is no residual-range versus angle ambiguity issue present in the claimed frequency-offset modulation range division MIMO system.
    Type: Grant
    Filed: December 17, 2020
    Date of Patent: October 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Ryan Haoyun Wu, Douglas Alan Garrity, Maik Brett
  • Patent number: 11796635
    Abstract: The disclosure relates to a radar transceiver having a transmitter comprising a phase shifter.
    Type: Grant
    Filed: August 2, 2021
    Date of Patent: October 24, 2023
    Assignee: NXP USA, INC.
    Inventors: Birama Goumballa, Gilles Montoriol, Cristian Pavao Moreira, Dominique Delbecq
  • Patent number: 11798871
    Abstract: A semiconductor device substrate is provided. The substrate includes an embedded trace substrate (ETS) portion. The ETS portion includes a first conductive layer embedded in the ETS portion at a first major surface. A portion of the first conductive layer is patterned to form a signal line. A non-conductive layer is disposed between the first conductive layer and a second conductive layer second embedded in the ETS portion. A third conductive layer is formed over the first major surface of the ETS portion. The third conductive layer is configured to form a stripline with the signal line of the first conductive layer.
    Type: Grant
    Filed: August 21, 2020
    Date of Patent: October 24, 2023
    Assignee: NXP USA, INC.
    Inventors: Chee Seng Foong, Trent Uehling, Tingdong Zhou
  • Patent number: 11800585
    Abstract: Embodiments of a method and an apparatus for wireless communications are disclosed. In an embodiment, a method for wireless communications involves transmitting, by a first multi-link device (MLD) to a second MLD, a management frame on at least one of two links associated with the first MLD and the second MLD in a multi-link operation, receiving, by the second MLD from the first MLD, the management frame on at least one of the two links, and operating the second MLD according to the management frame received on at least one of the two links.
    Type: Grant
    Filed: July 28, 2021
    Date of Patent: October 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Liwen Chu, Manish Kumar, Hongyuan Zhang, Huiling Lou
  • Patent number: 11799470
    Abstract: An integrated circuit can comprise an output terminal, a power transistor having a first current electrode coupled to the output terminal and a second current electrode coupled to a power supply terminal, a driver having an output coupled to a control electrode of the power switch, a capacitor having a first terminal coupled to the output terminal and a second terminal coupled to a circuit node, a first low pass filter coupled between the circuit node and an input of the driver, the first low pass filter having a first cut off frequency, a set of current sources, and a second low pass filter coupled between the circuit node and an output of the set of current sources. The second low pass filter can have a second cut off frequency that is higher than the first cut off frequency.
    Type: Grant
    Filed: August 2, 2022
    Date of Patent: October 24, 2023
    Assignee: NXP B.V.
    Inventors: Juliette Angèle Vedelago, Pascal Kamel Abouda, Soufiane Serser
  • Patent number: 11797041
    Abstract: One example discloses a power management circuit, including: a voltage reference circuit including a bandgap circuit coupled to and configured by a first trimming circuit; an undervoltage lockout (UVLO) circuit coupled to and configured by a second trimming circuit; wherein the first trimming circuit and the second trimming circuit are configured to receive a single trim control setting.
    Type: Grant
    Filed: April 8, 2022
    Date of Patent: October 24, 2023
    Assignee: NXP USA, Inc.
    Inventor: Trevor Mark Newlin
  • Patent number: 11797681
    Abstract: A system, method, and apparatus are provided for securely controlling operations of a data processing system by activating a security subsystem to control startup behavior of application subsystems, installing SMR parameters which include an initial authenticity proof for use with an initial verification process for the SMR and calculating an alternate authenticity proof for use with a subsequent verification process for the SMR, and then by subsequently verifying the SMR using the alternate authenticity proof for the subsequent verification process applied to the SMR so that the security subsystem can apply a comprehensive system reaction for the application subsystem based on the SMR verification results.
    Type: Grant
    Filed: June 8, 2021
    Date of Patent: October 24, 2023
    Assignee: NXP USA, Inc.
    Inventors: Fabrice Poulard, Marius Rotaru, Sören Heisrath